Patents by Inventor Fabrice Letertre

Fabrice Letertre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080248631
    Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 9, 2008
    Inventors: Fabrice Letertre, Yves Mathieu Le Vaillant, Eric Jalaguier
  • Publication number: 20080248251
    Abstract: A semiconductor substrate that includes a relatively thin monocrystalline useful layer, an intermediate layer transferred from a source substrate, and a relatively thick layer of a support present on one of the useful layer of the intermediate layer. The support is made of a deposited material that has a lower quality than that of one or both of the intermediate and useful layers. A bonding layer may be included on one of the intermediate layer or the useful layer, or both, to facilitate bonding of the layers an a thin layer may be provided between the useful layer and intermediate layer. These final substrates are useful in optic, electronic, or optoelectronic applications.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 9, 2008
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Patent number: 7422958
    Abstract: A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front face of the support substrate and into the cavities; polishing the layer to provide a perfectly planar surface; bonding a source substrate to the planar surface of the support substrate; withdrawing a portion of the source substrate to provide an assembly having a thin useful or active layer upon the insulating layer of the support substrate; and heat treating the assembly in a selected atmosphere at a temperature and for a time sufficient to diffuse atoms from the insulating layer and through the thin layer to reduce the thickness of the insulating layer while retaining the insulating material in the cavities of the support substrate.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 9, 2008
    Assignees: S.O.I.Tec Silicon on Insulator Technologies, Commissariat a l'Energie Atomique
    Inventors: Marek Kostrzewa, Fabrice Letertre
  • Patent number: 7422957
    Abstract: Methods for fabricating final substrates for use in optics, electronics, or optoelectronics are described. The method includes forming a zone of weakness beneath a surface of a source substrate to define a transfer layer; detaching the transfer layer from the source substrate along the zone of weakness; depositing a useful layer upon the transfer layer; and depositing a support material on the useful layer to form the final substrate. The useful layer may be deposited on the transfer layer before or after detaching the transfer layer from the source substrate. The useful layer is typically made of a material having a large band gap, and comprises at least one of gallium nitride, or aluminum nitride, or of compounds of at least two elements including at least one element of aluminum, indium, and gallium. The zone of weakness may advantageously be formed by implanting atomic species into the source substrate.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: September 9, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Publication number: 20080210975
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Application
    Filed: September 10, 2007
    Publication date: September 4, 2008
    Applicant: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Publication number: 20080191239
    Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.
    Type: Application
    Filed: September 5, 2007
    Publication date: August 14, 2008
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventor: Fabrice Letertre
  • Publication number: 20080194084
    Abstract: The invention relates to a method for fabricating a composite structure having heat dissipation properties greater than a bulk single crystal silicon structure having the same dimensions. The structure includes a support substrate, a top layer and an oxide layer between the support substrate and the top layer.
    Type: Application
    Filed: July 6, 2007
    Publication date: August 14, 2008
    Inventors: Oleg Kononchuk, Fabrice Letertre, Robert Langer
  • Patent number: 7407869
    Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaph on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: August 5, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre, Carlos Mazure
  • Patent number: 7404870
    Abstract: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: July 29, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Olivier Rayssac
  • Patent number: 7405135
    Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: July 29, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Publication number: 20080153251
    Abstract: A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front face of the support substrate and into the cavities; polishing the layer to provide a perfectly planar surface; bonding a source substrate to the planar surface of the support substrate; withdrawing a portion of the source substrate to provide an assembly having a thin useful or active layer upon the insulating layer of the support substrate; and heat treating the assembly in a selected atmosphere at a temperature and for a time sufficient to diffuse atoms from the insulating layer and through the thin layer to reduce the thickness of the insulating layer while retaining the insulating material in the cavities of the support substrate.
    Type: Application
    Filed: June 21, 2007
    Publication date: June 26, 2008
    Inventors: MAREK KOSTRZEWA, Fabrice Letertre
  • Publication number: 20070287273
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Application
    Filed: August 17, 2007
    Publication date: December 13, 2007
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
  • Publication number: 20070269960
    Abstract: A method for fabricating a semiconductor substrate. In an embodiment, this method includes the steps of transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on a support substrate.
    Type: Application
    Filed: July 31, 2007
    Publication date: November 22, 2007
    Applicant: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7288430
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: October 30, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technolgoies
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Patent number: 7279779
    Abstract: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: October 9, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7265029
    Abstract: Methods for fabricating a semiconductor substrate. In an embodiment, the technique includes providing an intermediate support, providing a nucleation layer, and providing at least one bonding layer between the intermediate support and the nucleation layer to improve the bonding energy therebetween, and to form an intermediate assembly. The method also includes providing at least one layer of a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited semiconductor material to form a final support assembly comprising the target substrate, the deposited semiconductor material, and the intermediate assembly, and processing the final support assembly to remove the intermediate assembly. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on the target substrate.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: September 4, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7262113
    Abstract: Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the invention relates to a method for recycling of a silicon carbide source substrate by removal of the excess zone followed by a finishing step to prepare the source substrate for recycling and reuse. Preferably, the excess zone is removed by a thermal budget where the temperature and time of such treatment causes exfoliation of the excess zone. The finishing step is performed in a manner to provide the desired surface roughness for the substrate so that it can be recycled for re-use. The technique includes implanting at least H+ ions through a front face of a source substrate of silicon carbide with an implantation energy E greater than or equal to 95 keV and an implantation dose D chosen to form an optimal weakened zone near a mean implantation depth, the optimal weakened zone defining the useful layer and a remainder portion of the source substrate.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: August 28, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Patent number: 7256101
    Abstract: Methods for preparing a semiconductor assembly are disclosed. In an implementation, the technique includes providing a support substrate and a bonding surface thereon, providing a donor substrate having a weakened zone that defines a useful layer and a bonding surface on the useful layer, and providing an interface layer of a predetermined material on the bonding surface of either the support substrate or the useful layer to provide a bonding surface thereon. The method also includes molecularly bonding the bonding surface of the interface layer to the bonding surface of the other of the support substrate or the useful layer to form a separable bonding interface therebetween, and to thus form the semiconductor assembly, and heat treating the semiconductor assembly to a temperature of at least 1000 to 1100° C.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 14, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Publication number: 20070148915
    Abstract: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the interface ring, and providing at least one controllable low-pressure zone in the vicinity of at least one of the first surface and the second surface. The technique also includes supplying the high-pressure zone with a controllable high-pressure force, and attacking the interface ring with at least one mechanical force in combination with the high-pressure force to cut the assembly.
    Type: Application
    Filed: March 2, 2007
    Publication date: June 28, 2007
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.,
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Patent number: 7235462
    Abstract: A method is provided for fabricating a substrate for optics, electronics, or opto-electronics. This method includes the steps of implanting atomic species into a face of a source substrate to form a weakened zone therein corresponding to the depth of penetration of the atomic species; transferring the seed layer on to a support substrate by bonding a face of the support substrate to the face of the source substrate and detaching the seed layer from the source substrate; depositing a working layer on the seed layer to form a composite substrate comprising the support substrate, seed layer and working layer; and detaching the seed layer and the working layer from the support substrate to form a substrate. Advantageously, the support substrate comprises a material having a thermal expansion value of about 0.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: June 26, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen