Patents by Inventor Fabrice Paillet

Fabrice Paillet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11757357
    Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Takao Oshita, Fabrice Paillet, Rinkle Jain, Jad Rizk, Danny Bronstein, Ahmad Arnaot
  • Patent number: 11747371
    Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Nachiket Desai, Harish Krishnamurthy, Suhwan Kim, Fabrice Paillet
  • Publication number: 20230208437
    Abstract: A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Sami Hyvonen, Fabrice Paillet, James Keith Hodgson, Anand Ramasundar, Cary Renzema, George Matthew, Sergio Carlo Rodriguez, Po-Cheng Chen, Sandeep Chilka, Bharadwaj Soundararajan
  • Publication number: 20230205244
    Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Anand Ramasundar, Cary Renzema, Fabrice Paillet, James Keith Hodgson, Po-Cheng Chen, Sergio Carlo Rodriguez, Harish K. Krishnamurthy, Jason Muhlestein
  • Publication number: 20230208432
    Abstract: An apparatus, system, and method for digital-to-analog (converter) control are provided. A DAC includes a first resistor ladder including a plurality of first electrical taps into different portions of the first resistor ladder, first and second pass gate trees coupled to receive outputs from the first electrical taps, first and second buffers coupled to receive outputs from the first and second pass gate trees, respectively, a second resistor ladder coupled to receive and be biased by outputs of the first and second buffers, the second resistor ladder including a plurality of second electrical taps into different portions of the second resistor ladder, and third, fourth, and fifth pass gate trees coupled to receive outputs from the second electrical taps.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Fabrice Paillet, Jason Muhlestein, James Keith Hodgson, SHIVADARSHAN BIDADI RAJEURS, George Matthew, Anand Ramasundar, Cary Renzema, Po-Cheng Chen, Sergio Carlo Rodriguez, Seng Rou Tey
  • Publication number: 20230168705
    Abstract: Embodiments herein relate to a feedback loop in a digital voltage regulator for controlling an output voltage. To avoid instability at light current loads, a gain of the loop is reduced as a power gate code indicates a reduced number of branches in set of current sources are enabled. In an example implementation, the code is classified into one range of a number of ranges, and the gain is set based on the one range. The gain can decrease each time the code enters a lower range, as indicated by the code crossing a threshold or predetermined value. For example, the gain can decrease by half each time the code enters a lower range.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: Sergio Carlo Rodriguez, Cary D, Renzema, Amit K. Jain, Po-Cheng Chen, Fabrice Paillet, Anand Ramasundar, James Keith Hodgson
  • Patent number: 11658570
    Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Harish Krishnamurthy, Sheldon Weng, Nachiket Desai, Suhwan Kim, Fabrice Paillet
  • Publication number: 20230092022
    Abstract: An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Fabrice Paillet, Anand Ramasundar, Khondker Ahmed, Harish K. Krishnamurthy, Cary Renzema, Christopher Mandic, James Keith Hodgson
  • Patent number: 11429173
    Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Chee Lim Nge, Amit Jain, Anant Deval, Nimrod Angel, Fabrice Paillet, Michael Zelikson, Sergio Carlo Rodriguez
  • Publication number: 20220239222
    Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
    Type: Application
    Filed: April 6, 2022
    Publication date: July 28, 2022
    Inventors: Takao Oshita, Fabrice Paillet, Rinkle Jain, Jad Rizk, Danny Bronstein, Ahmad Arnaot
  • Patent number: 11323026
    Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Takao Oshita, Fabrice Paillet, Rinkle Jain, Jad Rizk, Danny Bronstein, Ahmad Arnaot
  • Publication number: 20220113751
    Abstract: A reduced-size replica of power gate transistors may be used within a closed-loop voltage regulator to measure the average current delivered by the transistors in the non-replica power gate. The measured current is compared against a known reference current, and a feedback loop is used to modify the gate bias of the power gate and replica power gate transistors. An improved current sensing power gate replica solution may include measuring current from a small replica of the power gate and extrapolating the total current by digitally multiplying the replica current by the ratio of the size of the enabled power gates to the size of the replicas. The current through the replicas, which substantially matches the current in equivalent power gate devices, may be collected on an analog bus and conducted across a known resistor to generate a voltage that determines an estimated current of the power gate devices.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: James Keith Hodgson, Fabrice Paillet, Christopher J. Mandic, Cary Renzema, Anand Ramasundar, Sami Hyvonen, Po-Cheng Chen, Alex Santiago Rodriguez, Sergio Carlo Rodriguez, Saravanan Ramamoorthy, Ruthvin Jeevan Suvarna
  • Publication number: 20220069703
    Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 3, 2022
    Applicant: Intel Corporation
    Inventors: Harish Krishnamurthy, Sheldon Weng, Nachiket Desai, Suhwan Kim, Fabrice Paillet
  • Publication number: 20220065901
    Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Applicant: Intel Corporation
    Inventors: Nachiket Desai, Harish Krishnamurthy, Suhwan Kim, Fabrice Paillet
  • Patent number: 11204766
    Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Jason Seung-Min Kim, Nitin N. Garegrat, Anitha Loke, Nasima Parveen, David Y. Fang, Kursad Kiziloglu, Dmitry Sergeyevich Lukiyanchenko, Fabrice Paillet, Andrew Yang
  • Publication number: 20210075316
    Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Takao Oshita, Fabrice Paillet, Rinkle Jain, Jad Rizk, Danny Bronstein, Ahmad Arnaot
  • Publication number: 20190384603
    Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Jason Seung-Min Kim, Nitin N. Garegrat, Anitha Loke, Nasima Parveen, David Y. Fang, Kursad Kiziloglu, Dmitry Sergeyevich Lukiyanchenko, Fabrice Paillet, Andrew Yang
  • Patent number: 10367409
    Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 30, 2019
    Assignee: INTEL CORPORATION
    Inventors: Gerhard Schrom, Narayanan Raghuraman, Fabrice Paillet
  • Publication number: 20190146569
    Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Chee Lim NGE, Amit JAIN, Anant DEVAL, Nimrod ANGEL, Fabrice PAILLET, Michael ZELIKSON, Sergio Carlo RODRIGUEZ
  • Patent number: 9921592
    Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Joseph Shor, George L. Geannopoulos, Fabrice Paillet, Lan D. Vu, Oleg Dadashev