Patents by Inventor Fan Ren

Fan Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5903037
    Abstract: It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: May 11, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Alfred Yi Cho, Minghwei Hong, James Robert Lothian, Joseph Petrus Mannaerts, Fan Ren
  • Patent number: 5821171
    Abstract: A high quality interface between a GaAs-based semiconductor and a Ga.sub.2 O.sub.3 dielectric an be formed if the semiconductor surface is caused to have less than 1% of a monolayer impurity coverage at completion of the first monolayer of the Ga.sub.2 O.sub.3 on the surface. This is achieved, for instance, by preparing the surface of a GaAs wafer under UHV conditions in a first growth chamber, transferring the wafer through a transfer module under UHV to a second growth chamber that is also under UHV, and growing the dielectric by evaporation of Ga.sub.2 O.sub.3 from a solid source, the process carried out such that the integrated impurity exposure of the surface is at most 100 Langmuirs. Articles according to the invention have low interface state density (<10.sup.11 /cm.sup.2 .multidot.eV) and interface recombination velocity (<10.sup.4 cm/s). Semiconductor/Ga.sub.2 O.sub.3 structures according to the invention can be used advantageously in a variety of electronic or optoelectronic devices, e.g.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: October 13, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Minghwei Hong, Jueinai Raynien Kwo, Joseph Petrus Mannaerts, Matthias Passlack, Fan Ren, George John Zydzik
  • Patent number: 5777578
    Abstract: The global positioning system (GPS) compass is consisted of three main units. These units are the pointer, the sensor, and the controller. The pointer unit is comprised of an iron frame, an aluminum bar, and two aluminum plates. The sensor unit is comprised of global positioning system (GPS) receivers and global positioning system (GPS) antennas. The controller unit includes a personal computer, a stepping motor, several data interface circuit boards, and some motor control circuit boards. The baseline of the pointer is an aluminum bar of about one meter long. The sensor unit can measure the baseline's azimuth angle relative to the local coordinate. When command is received, the controller unit is capable of turning the aluminum bar to the desired direction by the aid of the stepping motor. There are two modes for operation available. One is the initial mode, the other is the normal mode. It takes about one or two minutes to complete the initial mode operation.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: July 7, 1998
    Assignee: National Science Council
    Inventors: Fan-Ren Chang, Li-Sheng Wang, Chi-Hsuan Tu, Yen-Weay Shei, Kun-Yuan Tu, Ching-Di Chang
  • Patent number: 5668049
    Abstract: In a method of making a GaAs-based semiconductor laser, a fully processed wafer is cleaved, typically in the ambient atmosphere, into laser bars, the laser bars are loaded into an evacuable deposition chamber (preferably an ECR CVD chamber) and exposed to a H.sub.2 S plasma. Following the exposure, the cleavage facets are coated in the chamber with a protective dielectric (preferably silicon nitride) layer. The method can be practiced with high through-put, and can yield lasers (e.g., 980 nm pump lasers for optical fiber amplifiers) capable of operation at high power.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: September 16, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Utpal Kumar Chakrabarti, William Scott Hobson, Fan Ren, Melinda Lamont Schnoes
  • Patent number: 5620909
    Abstract: A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: April 15, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Jenshan Lin, James R. Lothian, Fan Ren
  • Patent number: 5527425
    Abstract: In-containing III/V semiconductor materials (e.g., InGaP) can be dry etched in BCl.sub.3 in ECR apparatus. We have discovered that addition of N.sub.2 to the BCl.sub.3 can result in substantially higher etch rate (e.g., more than 50% higher). Etching is substantially without incubation period, and the resulting surface can be very smooth (e.g., RMS roughness less than 5 nm, even less than 2.5 nm). Exemplarily, the novel etching step is used in the manufacture of a InGaP/GaAs transistor.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: June 18, 1996
    Assignee: AT&T Corp.
    Inventors: William S. Hobson, John Lopata, Fan Ren
  • Patent number: 5459097
    Abstract: In accordance with the invention, aluminum-containing layers are grown by molecular beam processes using as an arsenic precursor phenylarsine (PhAs). Because PhAs is more reactive than arsine and less reactive than arsenic, it decomposes selectively on III-V surfaces but not on mask materials. Thus in contrast to conventional processes, growth using PhAs permits selective growth on unmasked gallium arsenide surfaces but inhibits growth on typical mask materials such as silicon nitride.
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: October 17, 1995
    Assignee: AT&T Corp.
    Inventors: Cammy R. Abernathy, Stephen J. Pearton, Fan Ren, Patrick W. Wisk
  • Patent number: 5227006
    Abstract: In accordance with the invention, gallium-containing layers are grown by molecular beam processes using as an arsenic precursor a compound of the dialkylaminoarsenic family (DAAAs) such as tris-dimethylamino arsenic (DMAAs). In contrast to conventional arsenic sources, DAAAs act as carbon "getters". When DAAAs are used as an arsenic source, the DAAAs getter carbon impurities from the gallium source. Thus, for example, DAAAs can be used as an arsenic source in combination with TMG as a gallium source to selectively grow high purity or n-type layers of gallium arsenide at low temperatures below 600.degree. C. In addition DMAAs has been found to be an excellent cleaning agent for gallium arsenide materials.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: July 13, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Cammy R. Abernathy, Stephen J. Pearton, Fan Ren, Patrick W. Wisk
  • Patent number: 5176792
    Abstract: The present applicants have discovered that a layer predominantly comprising tungsten can be formed into precise patterns having substantially vertical walls by using titanium as a mask and plasma etching in a fluorine-containing plasma such as CF.sub.4 or SF.sub.6. The success of the process is believed attributable to the occurrence of an etch stop reaction on the sidewalls of the tungsten. The products of the reaction inhibit horizontal etching. After the tungsten is etched, the titanium mask can be selectively removed, as by etching in dilute HF. Each step in the process can be effected without subjecting the workpiece to voltage magnitudes in excess of 200 volts or temperatures outside the range between room temperature and 200.degree. C.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: January 5, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Thomas R. Fullowan, Stephen J. Pearton, Fan Ren
  • Patent number: 5171704
    Abstract: High carrier concentration, as well as abrupt change in such concentration in GaAs-based devices, is the consequence of selection of tin dopant-containing precursor compounds as used during layer growth. Alkyl tin compounds, as used during MetalOrganic Molecular Beam Epitaxy, are of particular value in the growth of pnp heterojunction bipolar transistors, likely in conjunction with other devices in large scale integrated circuits.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: December 15, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Cammy R. Abernathy, Fan Ren
  • Patent number: 5168071
    Abstract: Disclosed is a method of making semiconductor devices that comprises etching of a semiconductor layer, with a patterned metal layer acting as the etch mask. The patterned metal layer comprises a mask metal layer (exemplarily Ti) overlying a contact metal layer (exemplarily a Au-containing layer). In an exemplary embodiment the inventive method is used to manufacture InP-based heterojunction bipolar transistors.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: December 1, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Thomas R. Fullowan, Stephen J. Pearton, Fan Ren
  • Patent number: 5106771
    Abstract: This invention is concerned with the production of Schottky barrier gate contacts in MESFET devices. The contact is produced by wet-chemical removal of native oxide in a sealed inert gas ambient and blow-drying the wet-etched surface with the inert gas prior to deposition of gate electrode metal on GaAs by electron beam evaporation in an inert gas ambient. Use of Pt, due to its higher metal work function, as the gate contact metal results in a Schottky barrier height of 0.98 eV for Pt on n-type GaAs. This is considerably higher than the barrier height of conventionally processed TiPtAu contacts (0.78 eV).
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: April 21, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Adrian B. Emerson, Fan Ren
  • Patent number: 4943540
    Abstract: A method for selectively etching higher aluminum concentration AlGaAs in the presence of lower aluminum concentration AlGaAs or GaAs, preferably at room temperature. The AlGaAs is first cleaned with a solution of NH.sub.4 OH and rinsed. The AlGaAs is then etched in a solution of HF. If photoresist is used on the AlGaAs, the photoresist may first be baked to increase the adhesion of the photoresist to the AlGaAs and to "toughen" the photoresist to reduce undercutting thereof. Agitation is applied to the AlGaAs or the etchant to assist in the uniform etching of the AlGaAs.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: July 24, 1990
    Assignee: AT&T Bell Laboratories
    Inventors: Fan Ren, Nitin J. Shah