Patents by Inventor Fang Mei

Fang Mei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11124489
    Abstract: Embodiments are directed to a series of novel EPAC antagonists that are designed, synthesized and evaluated in an effort to develop diversified analogues based on the scaffold of the previously identified high-throughput (HTS) hit ESI-09.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 21, 2021
    Assignee: Board of Regents, the University of Texas System
    Inventors: Jia Zhou, Zhiqing Liu, Na Ye, Fang Mei, Xiaodong Cheng
  • Publication number: 20200255388
    Abstract: Embodiments are directed to a series of novel EPAC antagonists that are designed, synthesized and evaluated in an effort to develop diversified analogues based on the scaffold of the previously identified high-throughput (HTS) hit ESI-09.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 13, 2020
    Applicant: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Jia ZHOU, Zhiqing Liu, Na Ye, Fang Mei, Xiaodong Cheng
  • Publication number: 20190296174
    Abstract: A photovoltaic device includes a substrate, a semiconductor stack and a transparent tunnel junction. The semiconductor stack includes an n-type layer selected from a first transparent conductive oxide layer, or a window layer, or both; and a p-type absorber layer disposed on the n-type layer, wherein the absorber layer consists essentially of CdSexTe(1-x), wherein x is from 1 to about 40 at. %. The transparent tunnel junction comprises a transparent interface layer of CdyZn(1-y)Te doped to be p+type, and a transparent contact layer doped to be n+type, and the interface layer is disposed between the p-type absorber layer and the transparent contact layer. In bifacial embodiments, the tunnel junction forms a transparent back contact and electrode; and in multi-junction embodiments, the tunnel junction forms a diode-like connector between top and bottom cells. The transparent contact layer may comprise tin oxide or zinc oxide doped with aluminum, fluorine or indium.
    Type: Application
    Filed: October 11, 2017
    Publication date: September 26, 2019
    Applicant: First Solar, Inc.
    Inventors: Markus Gloeckler, Fang Mei, Wei Zhang
  • Patent number: 9737512
    Abstract: Certain embodiments are directed to methods of treating pain, e.g., chronic or neuropathic pain, comprising administering an effective amount of an EPAC inhibitor.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 22, 2017
    Assignee: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Xiaodong Cheng, Fang Mei, Annemieke Kavelaars, Cobi J. Heijnen
  • Patent number: 9539256
    Abstract: Embodiments of the invention are directed to compounds that inhibit an activity of EP AC proteins and methods of using the same. The inventors have developed a sensitive and robust high throughput screening (HTS) assay for the purpose of identifying EPAC specific inhibitors (Tsalkova et al. (2012) PLOS ONE 7(1):e30441).
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: January 10, 2017
    Assignee: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Xiaodong Cheng, Jia Zhou, Tamara Tsalkova, Fang Mei, Haijun Chen
  • Publication number: 20160263088
    Abstract: Certain embodiments are directed to methods of treating pain, e.g., chronic or neuropathic pain, comprising administering an effective amount of an EPAC inhibitor.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 15, 2016
    Applicant: The Board of Regents of the University of Texas System
    Inventors: Xiaodong Cheng, Fang Mei, Annemieke Kavelaars, Cobi J. Heijnen
  • Publication number: 20150110809
    Abstract: Embodiments of the invention are directed to compounds that inhibit an activity of EP AC proteins and methods of using the same. The inventors have developed a sensitive and robust high throughput screening (HTS) assay for the purpose of identifying EPAC specific inhibitors (Tsalkova et al. (2012) PLOS ONE 7 (1):e30441).
    Type: Application
    Filed: February 8, 2013
    Publication date: April 23, 2015
    Applicant: The Board of Regents of the University of Texas System
    Inventors: Xiaodong Cheng, Jia Zhou, Tamara Tsalkova, Fang Mei, Haijun Chen
  • Patent number: 8993622
    Abstract: The present invention provides new antiviral compounds and pharmacological compositions comprising these new compounds and their use in the prophylaxis, prevention and treatment of viral infections, particularly adenovirus and herpes virus infections.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: March 31, 2015
    Assignee: Eirium AB
    Inventors: Göran Wadell, Karin Edlund, Marten Strand, Emma Andersson, Christopher Öberg, Mikael Elofsson, Ya-Fang Mei
  • Publication number: 20140348853
    Abstract: Embodiments of the invention are directed to compounds that inhibit an activity of EPAC proteins and methods of using the same.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Applicant: The Board of Regents of the University of Texas System
    Inventors: Bin Gong, Xiaodong Cheng, David Walker, Fang Mei
  • Publication number: 20130210915
    Abstract: The present invention provides new antiviral compounds and pharmacological compositions comprising these new compounds and their use in the prophylaxis, prevention and treatment of viral infections, particularly adenovirus and herpes virus infections.
    Type: Application
    Filed: June 13, 2011
    Publication date: August 15, 2013
    Inventors: Göran Wadell, Karin Edlund, Marten Strand, Emma Andersson, Christopher Öberg, Mikael Elofsson, Ya-Fang Mei
  • Publication number: 20130126974
    Abstract: An electrostatic discharge protection circuit is used in an integrated circuit with a first sub-circuit working with a first working voltage source and a second sub-circuit working with a second working voltage source lower than the first working voltage source. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor transistor of a first conductive type, having a drain thereof electrically connected to a pad of the integrated circuit, and gate, source and bulk thereof electrically connected to a bulk voltage; and a guard ring of the first conductive type, surrounding the first metal-oxide-semiconductor transistor of the first conductive type and coupled to the second working voltage source.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Ying-Hsuan WANG, Fang-Mei CHAO, Chia-Hsiang PAN, Yung-Chih SHIH
  • Patent number: 8426922
    Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: April 23, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Fang-Mei Chao, Ming-I Chen, Ying-Ko Chin, Yi-Chiao Wang
  • Patent number: 8415745
    Abstract: An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: April 9, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Fang-Mei Chao
  • Patent number: 8333843
    Abstract: The present disclosure relates to methods and related cleaning solutions (116) for cleaning a glass substrate (10, 112), such as for removing metal ion contaminates from a glass substrate (10, 112) having a transparent conductive oxide layer (12). One method includes: providing a glass substrate (10, 112) having a transparent conductive oxide (TCO) layer (12); and exposing the glass substrate (10, 112) to a cleaning solution (116) that includes 0.5% to 5% organic acid, wherein the organic acid used includes citric acid, acetic acid, or oxalic acid.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: December 18, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Fang Mei, David Tanner
  • Patent number: 8318559
    Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: November 27, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Ming-I Chen, Fang-Mei Chao
  • Publication number: 20120283318
    Abstract: The present invention concerns the field of gene therapy and in particular the use of specific adenoviral vector systems for gene therapy, said vector systems offering enhanced efficiency and specificity for gene delivery. More specifically, the present invention provides replicating-competent adenoviral vector systems carrying one or more inserted heterologous gene. The adenoviral vectors system according to the invention are characterized by high binding efficiency and infectivity to cells of neural origin, endothelial cells, carcinoma cells and dendritic cells.
    Type: Application
    Filed: October 4, 2010
    Publication date: November 8, 2012
    Inventors: Ya-Fang Mei, Goran Wadell
  • Patent number: 8225496
    Abstract: The present invention generally relates to a system that can be used to form a photovoltaic device, or solar cell, using processing modules that are adapted to perform one or more steps in the solar cell formation process. The automated solar cell fab is generally an arrangement of automated processing modules and automation equipment that is used to form solar cell devices. The automated solar fab will thus generally comprise a substrate receiving module that is adapted to receive a substrate, one or more absorbing layer deposition cluster tools having at least one processing chamber that is adapted to deposit a silicon-containing layer on a surface of the substrate, one or more back contact deposition chambers, one or more material removal chambers, a solar cell encapsulation device, an autoclave module, an automated junction box attaching module, and one or more quality assurance modules that are adapted to test and qualify the completely formed solar cell device.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: July 24, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Robert Z. Bachrach, Yong-Kee Chae, Soo Young Choi, Nicholas G. J. De Vries, Yacov Elgar, Eric A. Englhardt, Michel R. Frei, Charles Gay, Parris Hawkins, Choi (Gene) Ho, James Craig Hunter, Penchala N. Kankanala, Liwei Li, Wing Hoo (Hendrick) Lo, Danny Cam Toan Lu, Fang Mei, Stephen P. Murphy, Srujal (Steve) Patel, Matthew J. B. Saunders, Asaf Schlezinger, Shuran Sheng, Tzay-Fa (Jeff) Su, Jeffrey S. Sullivan, David Tanner, Teresa Trowbridge, Brice Walker, John M. White, Tae K. Won
  • Publication number: 20120091536
    Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Fang-Mei CHAO, Ming-I Chen, Ying-Ko Chin, Yi-Chiao Wang
  • Patent number: D654003
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: February 14, 2012
    Inventor: Fang-Mei Kuo
  • Patent number: D1024051
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng