Abstract: An integrated circuit package comprising a heat spreader; one or more substrate(s); one or more standoff(s); and one or more electronic component(s). One or more component(s) is/are coupled to a substrate and the substrate maybe coupled to a heat spreader. Standoff(s) are coupled on the heat spreader or substrates forming a cavity, and one or more component(s) and substrate(s) are located inside the cavity.

Abstract: Methods of forming secured substrates are presented. These methods involve creating signal-blocking vias and a series of meshes on various layers of an electronic substrate to mask signal traces and prevent tampering. By strategically positioning ground and power meshes on different layers, and optionally including dummy meshes, the method significantly increases the privacy and security of the electronic substrate. These techniques can also be applied inside or on integrated circuits to enhance security.

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

Abstract: Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.

Abstract: Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.

Abstract: An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

Abstract: An integrated circuit package comprising one or more electronic component(s); and one or more substrate(s), including a first substrate and a second substrate, wherein said first substrate including a first cavity on a first surface of said first substrate and a second cavity on a second surface of said first substrate, said second substrate includes a third cavity on a first surface of said second substrate and a fourth cavity on a second surface of said second substrate, said first substrate and said second substrate are stacked and coupled, and said one or more electronic component(s) is/are disposed inside said first cavity of first substrate and said fourth cavity of second substrate.

Abstract: A system in package comprising: one or more component(s); one or more heat spreader(s); and one or more substrate(s) having cavity(ies), wherein said cavity(ies) including a first cavity and a second cavity; said one or more component(s) is/are disposed within said first cavity and exposed to said second cavity; said one or more component(s) is/are coupled to said one or more substrate(s); and said one or more component(s) and said one or more substrate(s) are attached to said one or more heat spreader(s).

Abstract: An integrated circuit package comprising a heat spreader; one or more substrate(s); one or more standoff(s); and one or more electronic component(s). One or more component(s) is/are coupled to a substrate and the substrate maybe coupled to a heat spreader. Standoff(s) are coupled on the heat spreader or substrates forming a cavity, and one or more component(s) and substrate(s) are located inside the cavity.

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

Abstract: A sensor including one or more transistors; and one or more sensing elements, wherein an edge behaves as moving gate of said one or more transistors, an electric field is applied to said edge, said one or more transistors is/are biased, said one or more sensing elements is/are flexible, source and drain wells of said one or more transistors can be coplanar or stacked, said edge can move in a lateral or a parallel direction with respect to a transistor current, said edge can move in a vertical or a perpendicular direction with respect to said transistor current, and the magnitude of the change in said drain current determines the sensitivity.

Abstract: An electronic package comprising a first substrate that includes a first plurality of substrate vias and one or more cavities, a second substrate that includes a second plurality of substrate vias and one or more cavities, and a standoff substrate(s). The standoff substrate(s)positioned between the first and second substrate, the standoff substrate(s) is affixed to each of the first and second substrate, standoff substrate(s) forms a clearance between the first and second substrate, the standoff substrate(s) comprises an intervening plurality of substrate vias passing through the entire thickness of the standoff substrate(s), and a portion of the second plurality of substrate vias are configured to be or capable of being electrically connected to a portion of the first plurality of substrate vias by way of a portion of the intervening plurality of substrate vias.

Abstract: This invention describes the structure and function of an integrated multi-sensing system. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor, multi-axis gyroscope or accelerometer. The sensor uses a variety of different Field Effect Transistor technologies (horizontal, vertical, Si nanowire, CNT, SiC and III-V semiconductors) in conjunction with MEMS based structures such as cantilevers, membranes and proof masses integrated into silicon substrates. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electronic design.

Abstract: An integrated circuit package comprising one or more electronic component(s); and one or more substrate(s), including a first substrate and a second substrate, wherein said first substrate including a first cavity on a first surface of said first substrate and a second cavity on a second surface of said first substrate, said second substrate includes a third cavity on a first surface of said second substrate and a fourth cavity on a second surface of said second substrate, said first substrate and said second substrate are stacked and coupled, and said one or more electronic component(s) is/are disposed inside said first cavity of first substrate and said fourth cavity of second substrate.

Abstract: A system comprising a plurality of electronic components, wherein said plurality of electronic components including a first component and a second component, and said first component is a security component configured to generate and/or store security key(s); a substrate; one or more standoff substrate(s) comprising of cavity(3ies), wherein said one or more standoff substrate(s) is/are coupled to said substrate, said one or more standoff substrate(s) completely encircles said substrate, said security component is disposed inside said cavity(ies), said security component is coupled to said substrate, said security component is obfuscated by said substrate and said one or more standoff substrate(s), and said security component and said second component are configured to communicate security key(s) for performing device identification, authentication, encryption, and/or device integrity verification.

Abstract: An integrated circuit package comprising a first substrate having a cavity; a second substrate; and one or more semiconductor device(s) and/or passive component (s) are coupled to the second substrate. The cavity is formed using two opposite side walls of the first substrate where two opposite sides of the cavity are kept open, the one or more semiconductor device(s) and/or passive component(s) is/are electrically coupled using redistribution layers, and the second substrate is located inside the cavity of the first substrate.

Abstract: Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.

Abstract: Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads.

Abstract: An electronic package comprising a substrate, standoff substrate(s) and electronic components located within a clearance and/or one or more cavities. The substrate comprises substrate via(s) and/or substrate Redistribution Layer(s) and/or one or more cavities and/or substrate through hole(s). The standoff substrate(s) is coupled to said substrate. The standoff substrate(s) forms a clearance on the top and/or bottom surface of said substrate. The standoff substrate(s) comprises standoff substrate via(s) and/or standoff substrate Redistribution Layer(s). The standoff substrate via(s) and/or said standoff substrate Redistribution Layer(s) are coupled to said substrate Redistribution Layer(s) and/or said substrate via(s). The electronic components is coupled to said substrate and/or said at least one standoff substrate. The electronic components including a first electronic component and a second electronic component.

Abstract: Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.