Abstract: A system comprising a die stack having at least a first die and a second die; one or more Redistribution Layer(s); one or more Through Silicon Via(s); one or more Serial I/O(s); one or more contact pad(s); and a substrate. The die stack is configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s). The first die and/or said second die is/are configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s). The one or more Serial I/O(s) is/are configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s).

Abstract: An electronic package comprising a first substrate; a second substrate; at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first through-substrate vias by way of a portion of the intervening through-substrate vias; and at least three electronic components located within the clearance.

Abstract: This invention describes the structure and function of an integrated multi-sensing system. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor or accelerometer. The system uses Fabry-Perot Interferometer in conjunction with beam collimator, beam splitter, optical waveguide and a photodetector integrated. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electrostatic actuators.

Abstract: Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.

Abstract: A die stack having a second die is stacked vertically on top of a first die. A first plurality of test pads is located along a first edge of the first die. A second plurality of test pads is located along a second edge of the first die. The first edge of the first die is parallel to the second edge of the first die. A third plurality of test pads is located along a first edge of the second die. A fourth plurality of test pads is located along a second edge of the second die. The first edge of the second die is parallel to the second edge of the second die. The first edge of the first die and the second edge of the first die are perpendicular to the first edge of the second die and the second edge of the second die.

Abstract: This invention describes the structure and function of an integrated multi-sensing systems in stacked configuration. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor or accelerometer. The method uses Fabry-Perot Interferometer in conjunction with light source and a photodetector integrated in stacked configuration. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electrostatic actuators.

Abstract: An integrated circuit package comprising a first substrate having a cavity; a second substrate; and one or more semiconductor device(s) and/or passive component (s) are coupled to the second substrate. The cavity is formed using two opposite side walls of the first substrate where two opposite sides of the cavity are kept open, the one or more semiconductor device(s) and/or passive component(s) is/are electrically coupled using redistribution layers, and the second substrate is located inside the cavity of the first substrate.

Abstract: An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one or more semiconductor devices electrically coupled using redistribution layers, wherein the cavity is a first cavity, the substrate includes the first cavity and a second cavity, the one or more semiconductor devices are fully embedded within the first cavity of the substrate, the one or more semiconductor devices are fully embedded between the substrate and a first redistribution layer of said redistribution layers, bumps are fully embedded within the second cavity of the substrate, the bumps are fully embedded between the substrate and the first redistribution layer of said redistribution layers, and the first redistribution layer is fully embedded between the substrate and a semiconductor interposer.

Abstract: This invention describes the structure and function of an integrated multi-sensing system. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor, multi-axis gyroscope or accelerometer. The sensor uses a variety of different Field Effect Transistor technologies (horizontal, vertical, Si nanowire, CNT, SiC and III-V semiconductors) in conjunction with MEMS based structures such as cantilevers, membranes and proof masses integrated into silicon substrates. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electronic design.

Abstract: This invention describes the structure and function of an integrated multi-sensing systems in stacked configuration. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor or accelerometer. The method uses Fabry-Perot Interferometer in conjunction with light source and a photodetector integrated in stacked configuration. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electrostatic actuators.

Abstract: An electronic package including a first substrate, a second substrate, a first standoff substrate, and a second standoff substrate. A clearance is formed between the first standoff substrate, the second standoff substrate, the first substrate, and the second substrate. The first standoff substrate comprises an intervening plurality of TSVs passing through an entire thickness of the first standoff substrate. The second standoff substrate comprises an intervening plurality of TSVs passing through an entire thickness of the second standoff substrate. A portion of the second plurality of TSVs are electrically connected to a portion of the first TSVs by way of a portion of the intervening TSVs. A first electronic component disposed within the clearance and electrically coupled to the first substrate by a first plurality of electrical connections. A second electronic component disposed within the clearance and electrically coupled to one of the first substrate or the second substrate.

Abstract: Integrated circuits are described which directly connect a semiconductor interposer to a motherboard or printed circuit board by way of large pitch connections. A stack of semiconductor interposers may be connected directly to one another by a variety of means and connected to a printed circuit board through only a ball grid array of solder bumps. The stack of semiconductor interposers may include one or more semiconductor interposers which are shifted laterally to enable directly electrical connections to intermediate semiconductor interposers. The top semiconductor interposer may have no electrical connections on the top to increase security by making electrical “taps” much more difficult. An electrically insulating layer may be incorporated between adjacent semiconductor interposers and cavities or air gaps may also be included within one or more semiconductor interposers.

Abstract: This invention describes the structure and function of an integrated multi-sensing system. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor or accelerometer. The system uses Fabry-Perot Interferometer in conjunction with beam collimator, beam splitter, optical waveguide and a photodetector integrated. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electrostatic actuators.

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a semiconductor substrate and a TSV-less semiconductor interposer integrated on a substrate. The TSV-less semiconductor interposer has at least one semiconductor device assembled thereon, and the semiconductor devices are coupled to one another using redistribution layers. Wirebonding is used to electrically couple the TSV-less semiconductor interposer to the semiconductor substrate. Combination of Wirebonding, caveties, standoff-substrate and larger BGA balls are used to stacke assemblies.

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

Abstract: Integrated circuits are described which directly connect a semiconductor interposer to a motherboard or printed circuit board by way of large pitch connections. A stack of semiconductor interposers may be connected directly to one another by a variety of means and connected to a printed circuit board through only a ball grid array of solder bumps. The stack of semiconductor interposers may include one or more semiconductor interposers which are shifted laterally to enable directly electrical connections to intermediate semiconductor interposers. The top semiconductor interposer may have no electrical connections on the top to increase security by making electrical “taps” much more difficult. An electrically insulating layer may be incorporated between adjacent semiconductor interposers and cavities or air gaps may also be included within one or more semiconductor interposers.

Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.

Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.