Patents by Inventor Farhang Yazdani

Farhang Yazdani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Massively parallel interconnect fabric for complex semiconductor devices
    Patent number: 8390035
    Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: March 5, 2013
    Inventors: Majid Bemanian, Farhang Yazdani
  • Massively Parallel Interconnect Fabric for Complex Semiconductor Devices
    Publication number: 20120086050
    Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.
    Type: Application
    Filed: December 17, 2011
    Publication date: April 12, 2012
    Inventors: Majid Bemanian, Farhang Yazdani
  • Massively Parallel Interconnect Fabric for Complex Semiconductor Devices
    Publication number: 20120068229
    Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.
    Type: Application
    Filed: November 27, 2011
    Publication date: March 22, 2012
    Inventors: Majid Bemanian, Farhang Yazdani
  • Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via
    Publication number: 20110278737
    Abstract: Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.
    Type: Application
    Filed: July 27, 2011
    Publication date: November 17, 2011
    Inventor: Farhang Yazdani
  • Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
    Patent number: 8014166
    Abstract: Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.
    Type: Grant
    Filed: September 6, 2008
    Date of Patent: September 6, 2011
    Assignee: Broadpak Corporation
    Inventor: Farhang Yazdani
  • Massively Parallel Interconnect Fabric for Complex Semiconductor Devices
    Publication number: 20100283085
    Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.
    Type: Application
    Filed: May 6, 2009
    Publication date: November 11, 2010
    Inventors: Majid Bemanian, Farhang Yazdani
  • Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via
    Publication number: 20100058580
    Abstract: Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.
    Type: Application
    Filed: September 6, 2008
    Publication date: March 11, 2010
    Inventor: Farhang Yazdani