Patents by Inventor Fatih Hamzaoglu

Fatih Hamzaoglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194434
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Juan G. ALZATE VINASCO, Abhishek A. SHARMA, Fatih HAMZAOGLU, Bernhard SELL, Pei-Hua WANG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Chieh-Jen KU, Travis W. LAJOIE, Umut ARSLAN
  • Publication number: 20200091156
    Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Publication number: 20200035683
    Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Inte Corpooration
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Publication number: 20200020378
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
  • Publication number: 20200005866
    Abstract: Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Pulkit Jain, Umut Arslan, Fatih Hamzaoglu
  • Patent number: 10515697
    Abstract: Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Pulkit Jain, Umut Arslan, Fatih Hamzaoglu
  • Patent number: 10438640
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Publication number: 20190279697
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded ferroelectric random access memory (FeRAM) cells.
    Type: Application
    Filed: September 30, 2016
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Ilya KARPOV, Yih WANG, Fatih HAMZAOGLU, James CLARKE
  • Publication number: 20180342277
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 29, 2018
    Applicant: Intel Corporation
    Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
  • Patent number: 10068628
    Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Patent number: 9978447
    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Yih Wang, Muhammad M. Khellah, Fatih Hamzaoglu
  • Patent number: 9922691
    Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Pulkit Jain, Fatih Hamzaoglu, Liqiong Wei
  • Patent number: 9865322
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
  • Patent number: 9805790
    Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Nathaniel J. August, Pulkit Jain, Stefan Rusu, Fatih Hamzaoglu, Rangharajan Venkatesan, Muhammad Khellah, Charles Augustine, Carlos Tokunaga, James W. Tschanz, Yih Wang
  • Publication number: 20170229166
    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Inventors: Yih WANG, Muhammad M. KHELLAH, Fatih HAMZAOGLU
  • Patent number: 9666268
    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Yih Wang, Muhammad M. Khellah, Fatih Hamzaoglu
  • Publication number: 20170047105
    Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
    Type: Application
    Filed: March 5, 2016
    Publication date: February 16, 2017
    Inventors: PULKIT JAIN, FATIH HAMZAOGLU, LIQIONG WEI
  • Publication number: 20170018298
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
  • Patent number: 9478273
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
  • Patent number: 9455011
    Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
    Type: Grant
    Filed: March 25, 2012
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, David Kencke, Brian Doyle, Charles Kuo, James Tschanz, Fatih Hamzaoglu, Yih Wang, Roksana Golizadeh Mojarad