Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

Abstract: Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively.

Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

Abstract: Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively.

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

Abstract: A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.