Patents by Inventor Fawad Ahmed
Fawad Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240373255Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: July 8, 2024Publication date: November 7, 2024Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit KWAN, Yu YEUNG, Fawad AHMED, Tomas ŠEIRYS, Azim Ul ISLAM, Chun Kit CHAN, Ka Ho HO
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Publication number: 20240365105Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: June 27, 2024Publication date: October 31, 2024Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit KWAN, Yu YEUNG, Fawad AHMED, Tomas ŠEIRYS, Azim Ul ISLAM, Chun Kit CHAN, Ka Ho HO
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Publication number: 20240276199Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: April 22, 2024Publication date: August 15, 2024Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit KWAN, Yu YEUNG, Fawad AHMED, Tomas SEIRYS, Azim UI ISLAM, Chun Kit CHAN, Ka Ho HO
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Patent number: 12035154Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: GrantFiled: January 7, 2022Date of Patent: July 9, 2024Assignee: Pismo Labs Technology LimitedInventors: Uzair Ahmed Chughtai, Man Kit Kwan, Yu Yeung, Fawad Ahmed, Tomas {hacek over (S)}eirys, Azim Ui Islam, Chun Kit Chan, Ka Ho Ho
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Patent number: 12035412Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: GrantFiled: January 7, 2022Date of Patent: July 9, 2024Assignee: Pismo Labs Technology LimitedInventors: Uzair Ahmed Chughtai, Man Kit Kwan, Yu Yeung, Fawad Ahmed, Tomas {hacek over (S)}eirys, Azim Ul Islam, Chun Kit Chan, Ka Ho Ho
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Patent number: 11968745Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: GrantFiled: May 28, 2021Date of Patent: April 23, 2024Assignee: Pismo Labs Technology LimitedInventors: Uzair Ahmed Chughtai, Man Kit Kwan, Yu Yeung, Fawad Ahmed, Tomas {hacek over (S)}eirys, Azim Ul Islam, Chun Kit Chan, Kaho Ho Ho
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Publication number: 20240057176Abstract: The present invention discloses methods and systems for using one or more substitute connections between a cellular router and a server. When the server detects that one or more connections fail, the server starts using one or more substitute connections to the one or more failed connections. The connections are used to transmit requests and responses between the cellular router and the server. The requests comprise authentication requests that are transmitted to the server from the cellular router. The responses comprise authentication responses that are transmitted to the cellular router from the server. The authentication requests and the authentication responses are to authenticate one or more SIM cards housed in the server. The cellular router authenticates the one or more SIM cards by utilizing the authentication responses to keep maintaining respective cellular connections established using the one or more SIM cards from the server.Type: ApplicationFiled: May 28, 2021Publication date: February 15, 2024Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed Chughtai, Fawad Ahmed, Tomas Seirys, Man Kit Kwan, Al-Amin Quyyum, Yu Yeung, Ka Ho Ho
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Publication number: 20230354006Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: May 28, 2021Publication date: November 2, 2023Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit KWAN, Yu YEUNG, Fawad AHMED, Tomas SEIRYS, Azim Ul ISLAM, Chun Kit CHAN, Kaho Ho HO
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Publication number: 20220386102Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: January 7, 2022Publication date: December 1, 2022Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit KWAN, Yu YEUNG, Fawad AHMED, Tomas SEIRYS, Azim UI ISLAM, Chun Kit CHAN, Kaho Ho HO
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Publication number: 20220386148Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: January 7, 2022Publication date: December 1, 2022Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit KWAN, Yu YEUNG, Fawad AHMED, Tomas SEIRYS, Azim UI ISLAM, Chun Kit CHAN, Kaho Ho HO
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Publication number: 20220386103Abstract: The present invention discloses methods and systems for providing UICC/eUICC related response information to information requests at a cellular router. The method includes receiving an information request from a wireless communication module, and determining whether a response to the information request is cached. When the response information is not cached, forwarding the information request to a massive SIM apparatus (MSA). MSA will then respond to the information request. A response based on the MSA's response will then be sent to the wireless communication module for the information request. When the response information is cached, retrieve the response information and send it to the wireless communication module.Type: ApplicationFiled: January 7, 2022Publication date: December 1, 2022Applicant: Pismo Labs Technology LimitedInventors: Uzair Ahmed CHUGHTAI, Man Kit Kwan, Yu Yeung, Fawad Ahmed, Tomas Seirys, Azim UI Islam, Chun Kit Chan, Kaho Ho Ho
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Patent number: 10854611Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: May 15, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10847516Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: July 2, 2019Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190326292Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190267379Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10361204Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: June 12, 2018Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Slmsek-Ege, Diem Thy N. Tran
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Patent number: 10319724Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: July 12, 2018Date of Patent: June 11, 2019Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180331107Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: ApplicationFiled: July 12, 2018Publication date: November 15, 2018Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180301454Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: ApplicationFiled: June 12, 2018Publication date: October 18, 2018Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum SImsek-Ege, Diem Thy N. Tran
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Patent number: 10079235Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: July 31, 2017Date of Patent: September 18, 2018Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran