Patents by Inventor Fawad Ahmed

Fawad Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6693014
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Publication number: 20030054603
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Application
    Filed: November 1, 2002
    Publication date: March 20, 2003
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Patent number: 6482707
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: November 19, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Patent number: 6410951
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: June 25, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Publication number: 20010023948
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Application
    Filed: April 2, 2001
    Publication date: September 27, 2001
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Patent number: 6187618
    Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: February 13, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David A. Kao, Fawad Ahmed
  • Patent number: 6040208
    Abstract: A method of implanting dopants within an exposed first active region on a semiconductor substrate of a semiconductor wafer without doping an exposed second active region of the semiconductor substrate. A barrier wall is formed adjacent to the second active region and projects from the semiconductor substrate to a height above the second active region. A minimal angle relative to an axis perpendicular to the semiconductor substrate is determined at which doping ions directed at the semiconductor substrate must travel so that the barrier wall blocks the doping ions from contacting the second active region. The doping ions are used to bombard the semiconductor substrate at an angle at least as large as the minimal angle previously determined. As a result, the doping ions contact the first active region but do not substantially contact the second active region. The width of the second active region can be formed as greater than that of the first active.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: March 21, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey W. Honeycutt, Fernando Gonzalez, Fawad Ahmed
  • Patent number: 5907503
    Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: May 25, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David A. Kao, Fawad Ahmed
  • Patent number: 5896313
    Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.
    Type: Grant
    Filed: June 2, 1997
    Date of Patent: April 20, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David A. Kao, Fawad Ahmed