Abstract: Systems and methods are provided for edge bead removal. A laser beam of approximately a wavelength is received. The laser beam is delivered along a predetermined beam path. The laser beam is projected on an edge portion of a wafer for edge bead removal.

Abstract: A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer.

Abstract: A lithography cluster includes at least two lithography cells having a first lithography cell and a second lithography cell, an interface unit configured to integrate with the first lithography cell and the second lithography cell. The first lithography cell includes a first track and a first exposing tool and a second lithography cell includes a second track and a second exposing tool. The interface station includes a first interface buffer configured to couple the first track, a second interface buffer configured to couple the second track, a conveyor configured to couple the first interface buffer and the second interface buffer, and a robot configure to move along the conveyor, where in the robot transfers a substrate between functions of multiple functions within the first lithography cell, the second lithography cell, or between the first lithography cell and the second lithography cell.

Abstract: Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to generate a projection. In some embodiments, the non-correctable error image map is transformed via a feature extraction transform such as a Hough transform or a Radon transform. In some embodiments, the projection is compared to a set of rules to identify a signature in the non-correctable error image map indicative of a defect.

Abstract: The present disclosure provides a method that includes capturing a first image of a mask in a first exposure apparatus using a first exposure source and a first imaging sensor; capturing a second image of the mask in a second exposure apparatus using a second exposure source and a second imaging sensor; comparing the first image of the mask and the second image of the mask for a difference therebetween; and determining an action according to the difference.

Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.

Abstract: A lithography cluster includes at least two lithography cells having a first lithography cell and a second lithography cell, an interface unit configured to integrate with the first lithography cell and the second lithography cell. The first lithography cell includes a first track and a first exposing tool and a second lithography cell includes a second track and a second exposing tool. The interface station includes a first interface buffer configured to couple the first track, a second interface buffer configured to couple the second track, a conveyor configured to couple the first interface buffer and the second interface buffer, and a robot configure to move along the conveyor, where in the robot transfers a substrate between functions of multiple functions within the first lithography cell, the second lithography cell, or between the first lithography cell and the second lithography cell.

Abstract: An apparatus, method for manufacturing the apparatus, and method for processing a substrate using the apparatus are disclosed. An exemplary apparatus includes a substrate having a plurality of cells, wherein each cell includes a cell structure. The cell structure includes a piezoelectric film portion and a tip disposed over the piezoelectric film portion. The tip is physically coupled with the piezoelectric film portion.

Abstract: A method of determining overlay error. The method includes transferring a pattern from a reticle to a wafer and selecting a first set of data points to measure the positional difference between features on the reticle and features on the wafer. The method also includes determining a second set of data points characteristic of the first set of data points but containing fewer data points. A control system for using the second set of data points to dynamically adjust the position of the reticle.

Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.

Abstract: An apparatus, method for manufacturing the apparatus, and method for processing a substrate using the apparatus are disclosed. An exemplary apparatus includes a substrate having a plurality of cells, wherein each cell includes a cell structure. The cell structure includes a piezoelectric film portion and a tip disposed over the piezoelectric film portion. The tip is physically coupled with the piezoelectric film portion.

Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.

Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.

Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.

Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.

Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.

Abstract: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.

Abstract: A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask.

Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.

Abstract: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.