Patents by Inventor Fei-Gwo Tsai

Fei-Gwo Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080248404
    Abstract: A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 9, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Lang Chen, Tran-Hui Shen, Fei-Gwo Tsai, Chien-Chao Huang
  • Patent number: 7368229
    Abstract: A novel composite layer structure method which is suitable for reducing post-exposure delay (PED) effects associated with fabricating a photolithography reticle or mask and eliminating or at least minimizing variations between intended and realized critical dimension values for a circuit pattern fabricated on the reticle or mask. The method includes providing a mask blank having a metal layer, providing a photoresist layer on the metal layer of the mask blank, providing a protective layer on the photoresist layer and photo-cracking the photoresist layer in the desired circuit pattern typically by electron beam exposure. During subsequent post-exposure delay periods, the protective layer prevents or minimizes Q-time narrowing of the photo-cracked photoresist, and consequently, prevents or minimizes narrowing of the critical dimension of a circuit pattern etched in the metal layer according to the width of the photo-cracked photoresist.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: May 6, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lang Chen, Fei-Gwo Tsai
  • Patent number: 7244533
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: July 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Fei-Gwo Tsai
  • Patent number: 7241541
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: July 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Fei-Gwo Tsai
  • Publication number: 20070099098
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 3, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Fei-Gwo Tsai
  • Publication number: 20070099091
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 3, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Fei-Gwo Tsai
  • Publication number: 20070012335
    Abstract: A multi-step cleaning procedure cleans phase shift photomasks and other photomasks and Mo-containing surfaces. In one embodiment, vacuum ultraviolet (VUV) light produced by an Xe2 excimer laser converts oxygen to ozone that is used in a first cleaning operation. The VUV/ozone clean may be followed by a wet SC1 chemical clean and the two-step cleaning procedure reduces phase-shift loss and increases transmission. In another embodiment, the first step may use other means to form a molybdenum oxide on the Mo-containing surface. In another embodiment, the multi-step cleaning operation provides a wet chemical clean such as SC1 or SPM or both, followed by a further chemical or physical treatment such as ozone, baking or electrically ionized water.
    Type: Application
    Filed: July 18, 2005
    Publication date: January 18, 2007
    Inventors: Hsiao Chang, Tsun-Cheng Tang, Fei-Gwo Tsai, Tzu-Li Lee, Chien-Ming Chiu, Jang Lee, Yih-Chen Su, Chih-Cheng Lin, Tung Kang, Hung Hsieh
  • Patent number: 7160654
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Fei-Gwo Tsai
  • Patent number: 7043327
    Abstract: A lithographic apparatus for forming a patterned resist layer and a method for forming a microelectronic product both employ a lithographic exposure tool controller designed to: (1) receive input data for at least one non-environmental variable that influences an exposure dose when forming a patterned resist layer from a blanket resist layer while employing a lithographic exposure tool; and (2) determine the exposure dose for forming the patterned resist layer from the blanket resist layer while employing the input data. The apparatus and method provide for forming the microelectronic product with enhanced dimensional control.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 9, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei Gwo Tsai, Chun-Lang Chen, Cheng I Sun
  • Patent number: 7037628
    Abstract: The invention calculates an optimum etch recipe for etching a product pattern in an opaque material of a photolithographic exposure mask with the objective of achieving optimum CD performance of the product pattern. If, for this optimum etch recipe, the optimum CD performance cannot be achieved, dummy patterns are added to the mask that is used to etch the opaque material. If this latter approach still cannot achieve optimum CD performance, the product pattern to which the dummy pattern has been added is separated into two patterns such that one of these two patterns provides a Cr loading that assures optimum CD performance of the product pattern.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: May 2, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei-Gwo Tsai, Wei-Zen Chou, Zong-Xian Tsai
  • Publication number: 20050244721
    Abstract: A novel composite layer structure method which is suitable for reducing post-exposure delay (PED) effects associated with fabricating a photolithography reticle or mask and eliminating or at least minimizing variations between intended and realized critical dimension values for a circuit pattern fabricated on the reticle or mask. The method includes providing a mask blank having a metal layer, providing a photoresist layer on the metal layer of the mask blank, providing a protective layer on the photoresist layer and photo-cracking the photoresist layer in the desired circuit pattern typically by electron beam exposure. During subsequent post-exposure delay periods, the protective layer prevents or minimizes Q-time narrowing of the photo-cracked photoresist, and consequently, prevents or minimizes narrowing of the critical dimension of a circuit pattern etched in the metal layer according to the width of the photo-cracked photoresist.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Inventors: Chun-Lang Chen, Fei-Gwo Tsai
  • Publication number: 20050118514
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 2, 2005
    Inventor: Fei-Gwo Tsai
  • Publication number: 20050089765
    Abstract: The invention calculates an optimum etch recipe for etching a product pattern in an opaque material of a photolithographic exposure mask with the objective of achieving optimum CD performance of the product pattern. If, for this optimum etch recipe, the optimum CD performance cannot be achieved, dummy patterns are added to the mask that is used to etch the opaque material. If this latter approach still cannot achieve optimum CD performance, the product pattern to which the dummy pattern has been added is separated into two patterns such that one of these two patterns provides a Cr loading that assures optimum CD performance of the product pattern.
    Type: Application
    Filed: October 27, 2003
    Publication date: April 28, 2005
    Inventors: Fei-Gwo Tsai, Wei-Zen Chou, Zong-Xian Tsai
  • Patent number: 6841313
    Abstract: A photomask having dies relating to different functionalities is disclosed. A photomask for performing lithography in conjunction with fabrication of one or more semiconductor devices includes one or more first semiconductor dies and one or more second semiconductor dies. Each first semiconductor die relates to first functionality having a first definition grade. Each second semiconductor die relates to second functionality different than the first functionality. The second functionality has a second definition grade at least substantially close to the first definition grade. For instance, the second definition grade may be identical to the first definition grade, or it may be immediately adjacent (i.e., sequentially related) to the first definition grade.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: January 11, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei-Gwo Tsai, Yeou-Hsin Hsieh, Chih-Chiang Tu, Yu-Chin King
  • Patent number: 6799312
    Abstract: This invention provides a method of using an electron beam exposure system having an electron beam with a variable shape to form patterns in a layer of resist on a substrate, a mask substrate or an integrated circuit wafer, while maintaining adequate critical dimension control and beam stability. This is accomplished by setting the electron beam to a fixed square beam with a width set to provide optimum XY critical dimension control for exposing a frame pattern surrounding the original pattern. The frame pattern has a width of a first distance and surrounds the outer perimeter of the original pattern. This provides optimum XY critical dimension control at the outer perimeter of the original pattern. The remainder of the exposure field, which is the exposure field with the original pattern and the frame pattern subtracted away is exposed using an electron beam having a variable size and shape.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: September 28, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Fei-Gwo Tsai, Shy-Jay Lin
  • Publication number: 20030228047
    Abstract: Protecting the transparent substrate of a photomask when repairing opaque defects of the mask is disclosed. The photomask includes an opaque defect on a transparent substrate. The photomask is coated with photoresist. The mask is backside-exposed to a light source, to expose the photoresist where it is unblocked by the mask's opaque defect and other opaque regions. The photoresist is removed where it was unexposed to the light source. The opaque defect and the other opaque regions of the mask are exposed through the photoresist, but the transparent regions of the mask—where the transparent substrate does not have the opaque defect or the other opaque regions thereon—remain protected by the photoresist. The opaque defect is then removed, such as by using a focused ion beam (FIB). The photoresist over the exposed transparent substrate protects the substrate from riverbed effects and gallium staining.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 11, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Zen Chou, Chin-Wei Wen, Fei-Gwo Tsai
  • Publication number: 20030224148
    Abstract: A photomask having dies relating to different functionalities is disclosed. A photomask for performing lithography in conjunction with fabrication of one or more semiconductor devices includes one or more first semiconductor dies and one or more second semiconductor dies. Each first semiconductor die relates to first functionality having a first definition grade. Each second semiconductor die relates to second functionality different than the first functionality. The second functionality has a second definition grade at least substantially close to the first definition grade. For instance, the second definition grade may be identical to the first definition grade, or it may be immediately adjacent (i.e., sequentially related) to the first definition grade.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 4, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei-Gwo Tsai, Yeou-Hsin Hsieh, Chih-Chiang Tu, Yu-Chin King
  • Patent number: 6383693
    Abstract: A method for forming a patterned target layer from a blanket target layer while employing a blanket photoresist layer in conjunction with an exposure method which is susceptible to a proximity effect employs when exposing the blanket photoresist layer to form an exposed blanket photoresist layer a main latent pattern and a second latent pattern adjacent the main latent pattern. Each patterned photoresist layer formed upon developing the main latent pattern is formed of a first linewidth such that not all of a first portion of the blanket target layer formed therebeneath is etched within an isotropic etchant which is employed for etching the blanket target layer to form the patterned target layer.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: May 7, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsiao-Chen Wu, Fei-Gwo Tsai
  • Patent number: 6361911
    Abstract: A new method is provided for E-beam exposure. A new method is provided for variable shaped E-beam (VSB) and Gaussian laser and E-beam exposure systems. The conventional main pattern is, under the method of the invention involving VSB, surrounded on all sides by a dummy frame whereby the dummy frame limits the beam size of the exposure shots that are adjacent to the main pattern. All patterns that are created in this manner are therefore composites using the same exposure shot. This improves the CD uniformity of the pattern by reducing the shot linearity error for VSB exposure systems. For Gaussian beam exposure systems, the exposure shots are at times located exactly over the exposed figure. Typically, gray level is used to simulate the small figure, this however induces proximity effects. The method of the invention therefore also improves the proximity effect of the Gaussian beam exposure systems.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: March 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Fei-Gwo Tsai, Wei-Zen Chou