Patents by Inventor Fei Yu
Fei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130330033Abstract: One embodiment of the present invention provides a packaged optoelectronic module. The module includes a photonic chip having a top surface and a first substrate that includes a plurality of vias and a reflective surface. The photonic chip is flip-chip bonded to the first substrate with the top surface facing the first substrate. The vias facilitate electrical connections to the top surface, and the reflective surface forms an angle with the top surface, thereby enabling optical coupling between the top surface and an optical fiber placed in a direction that is substantially parallel to the top surface.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Fei Yu, Qi Deng
-
Patent number: 8597057Abstract: An electrical card connector for holding a card with a notch defined on a lateral side thereof, includes an insulative housing, a number of contacts and a push-push mechanism. The push-push mechanism includes a slider movable between an initial position and a final locking position along a front-to-back direction, a spring abutting against the slider and an elastic locking arm having a card lock for locking with the notch of the card. The slider further includes a rigid protrusion to engage with the notch of the card. The rigid protrusion not only helps the card lock hold the card when the slider is located at the final locking position, but also helps the card lock prevent the card from flying out of the card receiving space when the slider moves from the final locking position back to the initial position.Type: GrantFiled: January 6, 2012Date of Patent: December 3, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Jian-Fei Yu, Fang-Yue Zhu, Qi-Jun Zhao
-
Patent number: 8580698Abstract: A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.Type: GrantFiled: April 14, 2010Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yang Lee, Xiong-Fei Yu, Jian-Hao Chen, Cheng-Hao Hou, Da-Yuan Lee, Kuang-Yuan Hsu
-
Patent number: 8550781Abstract: A rotor includes a hub, rotary blades extending outwardly from the hub, and an annular wall surrounding the rotary blades. Each rotary blade includes a windward lateral surface and a leeward lateral surface at opposite sides thereof. The annular wall adjoins the outer ends of the rotary blades and is rotatable therewith. A perforation is defined in the annular wall between two neighboring rotary blades and adjacent to the leeward lateral surface of a leading rotary blade of the neighboring rotary blades.Type: GrantFiled: April 1, 2010Date of Patent: October 8, 2013Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Xin-Xiang Zha, Ye-Fei Yu, Jer-Haur Kuo
-
Patent number: 8546885Abstract: An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.Type: GrantFiled: July 25, 2011Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
-
Publication number: 20130245161Abstract: A resin composition includes (A) 100 parts by weight of epoxy resin; (B) 20 to 100 parts by weight of polybutadiene styrene divinylbenzene graft terpolymer resin; (C) 2 to 20 parts by weight of di-tert-butylhydroquinone (DTBHQ); (D) 5 to 50 parts by weight of polyphenyl ether modified cyanate ester resin; and at least one of (E) inorganic filler, (F) chain extending sealing agent, and (G) catalyst. The resin composition is characterized by specific ingredients and proportions thereof to attain high heat resistance, low dielectric constant Dk, and low dielectric dissipation factor Df, and being halogen-free, and therefore is applicable to protective film of printed circuit boards, insulating protective film of electronic components, and resin insulation film of leadframes.Type: ApplicationFiled: December 28, 2012Publication date: September 19, 2013Applicant: ELITE MATERIAL CO., LTD.Inventors: CHEN-YU HSIEH, YI-FEI YU
-
Publication number: 20130232869Abstract: The present invention provides for novel biochar compositions and a method for producing a new substrate for growing plants using the biochar and a method for growing plants using the biochar composition substrate.Type: ApplicationFiled: November 14, 2012Publication date: September 12, 2013Applicant: Mississippi State UniversityInventors: Fei Yu, Phillip H. Steele, Mengmeng Gu, Yan Zhao
-
Patent number: 8529298Abstract: An electronic card connector defining a receiving space for receiving an electronic card, includes an insulative housing, a number of contacts retain in the insulative housing, and a metal shell covering the insulative housing. The insulative housing has a bottom wall. The metal shell has a top wall opposed to the bottom wall, and a pair of side walls. The metal shell defines a depressed portion outwardly recessed from an intersection portion of the top wall and the side wall.Type: GrantFiled: July 12, 2010Date of Patent: September 10, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Fang-Yue Zhu, Jian-Fei Yu, Qi-Jun Zhao
-
Publication number: 20130207127Abstract: An integrated circuit package includes a substrate having a recess formed along at least a portion of a perimeter of the substrate, and an optical die having opto-electric circuitry, the optical die coupled to the substrate such that a portion of the optical die with the opto-electric circuitry overhangs the recess. The integrated circuit package also includes an optical unit disposed in the recess such that optical signals emitted by the opto-electric circuitry are reflected away from the substrate and incident optical signals are reflected onto the opto-electric circuitry.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: FutureWei Technologies, Inc.Inventors: Fei Yu, Qi Deng
-
Publication number: 20130186676Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: FutureWei Technologies, Inc.Inventors: Fei Yu, Anwar A. Mohammed, Rui Niu
-
Publication number: 20130100614Abstract: An electronic device includes a circuit board, a communication chip, a ceramic heat sink and an elastic fastener. The circuit board has first and second fixing members. The communication chip is disposed on the circuit board. The ceramic heat sink disposed on the communication chip has first and second lateral sides. The elastic fastener includes a first extension portion, a second extension portion and a clamping portion. The first extension portion extending to the first fixing member from the first lateral side is engaged with the first fixing member to generate a first fastening force. The second extension portion extending to the second fixing member from the second lateral side is engaged with the second fixing member to generate a second fastening force. The clamping portion applies a force on the ceramic heat sink to tightly press the ceramic heat sink on the communication chip.Type: ApplicationFiled: August 17, 2012Publication date: April 25, 2013Applicant: SERCOMM CORPORATIONInventors: Yi-Fei Yu, Yuan-Heng Huang
-
Publication number: 20130056836Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: September 1, 2011Publication date: March 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuan-Yuan Hsu, Jeff J. Xu
-
Patent number: 8382498Abstract: A card connector includes an insulative housing defining a card receiving space, a number of contacts retained in the insulative housing, an ejector received in the insulative housing and a metal shell covering the insulative housing. The ejector includes a movable slider, a spring, and a pin member, the slider defines a heart-shaped slot, and the pin member has a positioning end being rotatablely retained to the insulative housing and a free end being slidable along the heart-shaped slot to lock the slider. A latching piece is retained to the insulative housing and has a catching portion catching the pin member and an elastic portion connecting with the catching portion. When the pin member slides, the catching portion will bring the elastic portion to deflect and provide an outward or inward force to the pin member so as to control a movement trace of the pin member.Type: GrantFiled: May 31, 2011Date of Patent: February 26, 2013Assignee: Hon Hai Precision Ind. Co., LtdInventors: Jian-Fei Yu, Feng Zhou, Qi-Jun Zhao
-
Publication number: 20130032900Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.Type: ApplicationFiled: August 1, 2011Publication date: February 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao HOU, Wei-Yang LEE, Xiong-Fei YU, Kuang-Yuan HSU
-
Patent number: 8367563Abstract: A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.Type: GrantFiled: October 7, 2009Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Hui Ouyang, Da-Yuan Lee, Kuang Yuan Hsu, Hun-Jan Tao, Xiong-Fei Yu
-
Publication number: 20130026637Abstract: An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao HOU, Peng-Soon LIM, Da-Yuan LEE, Xiong-Fei YU, Chun-Yuan CHOU, Fan-Yi HSU, Jian-Hao CHEN, Kuang-Yuan HSU
-
Publication number: 20130017678Abstract: Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung TSAI, Xiong-Fei YU, Yu-Lien HUANG, Da-Wen LIN
-
Patent number: 8334197Abstract: The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.Type: GrantFiled: December 16, 2009Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Xiong-Fei Yu, Wei-Yang Lee, Matt Yeh
-
Patent number: 8334198Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: April 12, 2011Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hao Chen, Wei-Yang Lee, Wei-Yeh Tang, Xiong-Fei Yu, Kuang-Yuan Hsu
-
Patent number: 8323002Abstract: A heat dissipation device includes a heat sink, a cooling fan, an electric motor and a belt. The cooling fan includes a fan housing and an impeller. The impeller includes a hub, a plurality of fan blades and a shaft extending from the hub and having a distal end protruded out of the fan housing. A fan pulley is fixed to the distal end of the shaft. The electric motor includes a driving pulley. The belt has one end engaging with the driving pulley of the electric motor and an opposite end engaging with the fan pulley of the cooling fan. Rotation of the driving pulley of the electric motor is transferred to the fan pulley via the belt to cause the impeller to rotate.Type: GrantFiled: June 11, 2009Date of Patent: December 4, 2012Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Xin-Xiang Zha, Ye-Fei Yu, Jun Ding, Jer-Haur Kuo