Patents by Inventor Feng Chen

Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11997768
    Abstract: An LED filament comprising a plurality of LED filament units, each of the plurality of LED filament units includes a LED chip with an upper surface and a lower surface opposite to the upper surface of the LED chip, and a light conversion layer comprising a top layer and a base layer, and the base layer comprises an upper surface and a lower surface opposite to the upper surface of the base layer, where the top layer with an upper surface and a lower surface opposite to the upper surface of the top layer is disposed on at least two sides of each of the LED chips, the lower surface of each of the LED chips is close to the upper surface of the base layer, and the upper surface of the top layer is away from each of the LED chips.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: May 28, 2024
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Ai-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen
  • Patent number: 11994713
    Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
  • Patent number: 11992890
    Abstract: The invention provides an electrochemical discharge-assisted micro-grinding device for micro-components of brittle and hard materials. The device includes a micro-grinding tool, grinding fluid, a workpiece, an auxiliary electrode, a processing groove, and a pulsed DC power supply; the processing groove is filled with grinding fluid; the micro-grinding tool, the workpiece, and the auxiliary electrode are immersed in the grinding fluid; the micro-grinding tool is composed of a conductive grinding tool base, an electroplating layer, and insulated superabrasives. The micro-grinding tool is connected to the negative electrode of the pulsed DC power supply; the grinding fluid is composed of H2O2, Na2CO3, EDTA-Fe-Na, and deionized water; the workpiece material is brittle and hard; a large number of micro structures need to be produced on the surface of the workpiece.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: May 28, 2024
    Assignee: Changsha University of Science and Technology
    Inventors: Cong Mao, Ziyang Chen, Yinghui Ren, Wei Li, Yuanqiang Luo, Gang Wu, Mingjun Zhang, Kun Tang, Yongle Hu, Feng Shi, Weidong Tang, Ci Song
  • Patent number: 11996464
    Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: May 28, 2024
    Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., JIANGSU ADVANCED MEMORY SEMICONDUCTOR CO., LTD.
    Inventors: Chieh-Fang Chen, Kuo-Feng Lo, Chung-Hon Lam, Yu Zhu
  • Patent number: 11996323
    Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Publication number: 20240170314
    Abstract: A display device manufacturing apparatus includes a working platform, a transferring station including a transferring gantry and a transferring welding device, a defect inspecting station including an inspecting gantry and a defect inspecting device, and a mending station including a mending gantry and a mending device. The working platform includes a plurality of pairs of conveying paths, and a plurality of carriers disposed on the plurality of pairs of conveying paths. The transferring gantry, inspecting gantry and mending gantry are disposed on the working platform and stride over the conveying paths.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: TSAN-JEN CHEN, WEN-I LEE, TZU-HUNG HSU, QING-FENG PAN
  • Publication number: 20240168562
    Abstract: Glasses with gesture recognition function include a glasses frame and a gesture recognition system. The gesture recognition system is disposed on the glasses frame and configured to detect hand gestures in front of the glasses thereby generating a control command. The gesture recognition system transmits the control command to an electronic device to correspondingly control the electronic device.
    Type: Application
    Filed: January 15, 2024
    Publication date: May 23, 2024
    Inventors: HORNG-GOUNG LAI, EN-FENG HSU, MENG-HUAN HSIEH, YU-HAO HUANG, NIEN-TSE CHEN
  • Publication number: 20240164449
    Abstract: A vaporization assembly includes: a porous substrate; and a heating element. The porous substrate has a vaporization surface, and the heating element is arranged on the vaporization surface. The porous substrate includes a fence structure, and the fence structure surrounds the vaporization surface, defining an accommodating groove. In an embodiment, the fence structure is arranged on a peripheral edge of a vaporization end of the porous substrate, and an area of the vaporization end within the fence structure forms the vaporization surface.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 23, 2024
    Inventors: Bo LI, Feng CHEN, Bing CHEN, Hongming ZHOU, Jicai LONG, Wangsheng LIU
  • Publication number: 20240166049
    Abstract: Provided are a projection assembly, a display system and a vehicle. The projection assembly is applied to the vehicle, and the projection assembly includes: a housing, a bottom cover, a display module, a heat dissipation assembly and an imaging lens. The housing is connected with the bottom cover, and the housing and the bottom cover form an accommodating space, the heat dissipation assembly, the display module and the imaging lens are all disposed in the accommodating space, and the display module is disposed on the heat dissipation assembly; and the imaging lens includes a lens barrel and a lens assembly, the lens barrel is disposed on the heat dissipation assembly, the lens assembly is disposed in the lens barrel, and the lens barrel surrounds the display module, the display module faces the lens assembly, the housing is provided with an opening, and the lens assembly faces the opening.
    Type: Application
    Filed: September 2, 2021
    Publication date: May 23, 2024
    Inventors: Yuhong LIU, Chenru WANG, Yulong WU, Lili CHEN, Feng ZI
  • Publication number: 20240167044
    Abstract: Disclosed herein are methods and compositions for generation of cell lines to promote unnatural amino acid-containing protein production using genome engineering technology.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 23, 2024
    Applicant: Ambrx, Inc.
    Inventors: Sigeng CHEN, Yingchun LU, Feng TIAN
  • Publication number: 20240169615
    Abstract: An electronic device and a non-transitory computer-readable storage medium are provided. The electronic device includes a storage module and a processing module. The storage module is configured to store at least one program instruction. The processing module is coupled to the storage module, and is configured to load the at least one program instruction to perform the following steps: parsing a plurality of cells in an analysis area in a data sheet to identify each of the cells as a formula cell or a non-formula cell; classifying the formula cells so that the formula cells having similar formula expressions fall into the same formula group; analyzing a formula structure of the formula expressions of each formula group to output at least one recommended chart option.
    Type: Application
    Filed: April 3, 2023
    Publication date: May 23, 2024
    Applicant: POTIX CORPORATION
    Inventors: Chih-Heng Chen, Jen-Feng Chao, Wenning Hsu, Ming-Shia Yeh
  • Publication number: 20240170323
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240172278
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a station (STA). In certain configurations, the STA transmits a request-to-send (RTS) frame in an enhanced long range (ELR) format for obtaining a transmission opportunity (TXOP). The STA receives a first clear-to-send (CTS) frame in the ELR format or a non-ELR format responding to the RTS frame. In response to receiving the first CTS frame, the STA transmits data in the ELR format in the TXOP. In certain configurations, the STA further receives an acknowledgement in the same format as the first CTS frame for responding to the data being transmitted. In certain configurations, prior to transmitting the RTS frame, the STA transmits a CTS-to-Self frame in the non-ELR format.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: You-Wei Chen, Jianhan Liu, Kai ying Lu, Shuling Feng, Tsung-Hsuan Wu, Thomas Edward Pare, JR.
  • Publication number: 20240170534
    Abstract: A method for manufacturing a nanosheet semiconductor device includes: forming a liner layer to cover first and second fin structures, each of the fin structures including a stacked structure, a poly gate disposed on the stacked structure, and inner spacers, the stacked structure including sacrificial features covered by the inner spacers, and channel features disposed to alternate with the sacrificial features; forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that interconnects the upper and lower portions and that laterally covers the liner layer; subjecting the upper and lower portions to a directional treatment; and removing the upper and interconnecting portions of the dielectric layer and a portion of the liner layer, to form a liner and a bottom dielectric insulator disposed on the liner.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhi-Chang LIN, Ko-Feng CHEN, Chien-Ning YAO, Chien-Hung LIN
  • Publication number: 20240170343
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Publication number: 20240170385
    Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 23, 2024
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Mei-Yen CHEN, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
  • Patent number: 11989373
    Abstract: A circuit to cancel the effect of parasitic capacitances (“initial signals”) in calculations as to precise touch locations on a touch display screen (signal compensation circuit) includes first and second compensation circuits connected to a charge-discharge node. The first compensation circuit receives initial signals, generates first charging currents to charge, and first discharging currents to discharge, the charging-discharging node. The second compensation circuit generates second charging currents to charge, and second discharging currents to discharge, the charging-discharging node. Values of the first charging currents, the second charging currents, the first discharging currents, and the second discharging currents are of different magnitudes and are applied in order to amount to a more precise match for the exact compensation value required.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: May 21, 2024
    Assignee: JADARD TECHNOLOGY INC.
    Inventors: Feng-Wei Lin, Yu-Chieh Hsu, Long Chen
  • Patent number: 11991882
    Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 21, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yao-An Chung, Yuan-Chieh Chiu, Ting-Feng Liao, Kuang-Wen Liu, Kuang-Chao Chen
  • Patent number: 11990968
    Abstract: A RF module and an electronic device. The RF module includes a RF transceiver module; a first antenna configured to transmit a first transmission signal, and receive a first main reception signal and a second diversity reception signal; a first triplexer connected to the RF transceiver module and the first antenna, and being configured to isolate the first transmission signal, the first main reception signal, and the second diversity reception signal; a second antenna configured to transmit a second transmission signal, receive a second main reception signal and a first diversity reception signal, and a frequency band of the first transmission signal being different from that of the second transmission signal; and a second triplexer connected to the RF transceiver module and the second antenna, and being configured to isolate the second transmission signal, the second main reception signal, and the first diversity reception signal.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: May 21, 2024
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Feng Chen, Lin Tong
  • Patent number: 11990474
    Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu Fang Fu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Fu-Huan Tsai