Patents by Inventor Feng Chen

Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151320
    Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.
    Type: Application
    Filed: December 6, 2023
    Publication date: May 8, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi Chuen Eng, Tzu-Feng Chang, Teng-Chuan Hu, Yi-Wen Chen, Yu-Hsiang Lin
  • Publication number: 20250151330
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer. A lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: An-Hung TAI, Jian-Hao CHEN, Hui-Chi CHEN, Kuo-Feng YU
  • Publication number: 20250148988
    Abstract: An electronic device includes a substrate, a first transistor and a second transistor. The first transistor is disposed on the substrate and has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second transistor is disposed on the substrate and has a first terminal electrically connected to the second terminal of the first transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first transistor. Wherein a voltage value of the first voltage level is greater than a voltage value of the second voltage level.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: Lien-Hsiang CHEN, Kung-Chen KUO, Ming-Chun TSENG, Cheng-Hsu CHOU, Kuan-Feng LEE
  • Publication number: 20250151088
    Abstract: An apparatus includes a receiver configured to receive, from a base station, a control message indicating a sidelink resource pool. The apparatus further includes a transmitter configured to perform, after receiving the control message, a sidelink transmission using one or more sidelink resources. Based on a speed exceeding a threshold speed, the one or more sidelink resources include one of a first sidelink resource of the sidelink resource pool or a preconfigured sidelink resource. The one or more sidelink resources include the first sidelink resource based on the first sidelink resource being associated with a high speed flag. The one or more sidelink resources include the preconfigured sidelink resource based on a time interval since a previous sidelink transmission failing to exceed a threshold time interval and further based on the sidelink resource pool failing to indicate a resource associated with the high speed flag.
    Type: Application
    Filed: April 28, 2022
    Publication date: May 8, 2025
    Inventors: Chunxia Li, Matthew Heng Zhang, Rajat Kapur, Yuyu Yan, Liang Zhu, Hua Xu, Feng Chen, Ankit Gothi
  • Publication number: 20250149509
    Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 8, 2025
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu, Ping-Tzu Chen, Che-Wei Chen
  • Publication number: 20250145040
    Abstract: A method for monitoring an electric vehicle charging apparatus is provided. A charging pile that includes a power meter and a processor is used to provide a charging current to an electric vehicle through a charging connector. The power meter detects the charging current to generate an initial current value and an initial power value that correspond to an initial charging time, and a present current value and a present power value that correspond to a present time, so that the processor calculates an initial resistance value and a present resistance value of the charging connector accordingly, and then calculates an estimated present temperature value of the charging connector based on the initial resistance value and the present resistance value. The estimated present temperature value is compared with an over-temperature threshold to determine whether to reduce the charging current.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Inventors: Hsien-Ju WU, Chun-Chieh CHIU, Tai-Chang CHEN, Jinn-Feng JIANG, Chia-Lung HUANG, Mei-Jung CHEN
  • Publication number: 20250147219
    Abstract: A front light module configured to be disposed on a display panel to illuminate the display panel is provided. The front light module includes a light source and a light guide plate. The light guide plate has a first surface facing away from the display panel, a second surface facing the display panel, and a light incident surface facing the light source. The light incident surface connects the first surface and the second surface. The first surface has multiple sets of optical micro-structures. Each of the sets of the optical micro-structures includes multiple optical micro-structures disposed or distributed asymmetrically.
    Type: Application
    Filed: October 9, 2024
    Publication date: May 8, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chia Feng Ho, Jen-Yuan Chi, Yu-Nan Pao, Yen-Hao Chen, Yu-Chuan Wen, Hsin-Tao Huang
  • Publication number: 20250149485
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Patent number: 12293947
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Fu-Sheng Li, Tsai-Jung Ho, Bor Chiuan Hsieh, Guan-Xuan Chen, Guan-Ren Wang
  • Patent number: 12295079
    Abstract: To provide a safer over voltage protection, it is provided a driving circuit for a light emitting source, comprising an input adapted to receive a power supply; a conversion circuit, adapted to convert the power supply and provide a converted power, comprising a power switch (M2); an output, adapted to output the converted power; an output capacitor (C2) connected at the output; a first control circuit coupled to the output and connected to the power switch (M2), adapted to sense a voltage corresponding to the voltage on the output capacitor and control the power switch operate in a power-reducing mode to reduce the converted power when the voltage corresponding to the voltage on the output capacitor sensed by the first control circuit exceeds a first level; and a second control circuit (D15) connected to the output capacitor (C2) and connected to a control terminal of the power switch (M2), adapted to sense a voltage at the output capacitor (C2) and damage and make the power switch (M2) unoperational permane
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: May 6, 2025
    Assignee: SIGNIFY HOLDING, B.V.
    Inventors: Jie Fu, Shiguang Sun, Zhiquan Chen, Feng Ju, Yu Wang, Gang Wang
  • Patent number: 12291795
    Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: May 6, 2025
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Hong-Huei Huang, Benjamin Michael Meyer, Chun-Sheng Wu, Wei-Chen Chou, Chen-Yi Lin, Feng-Chien Tsai
  • Patent number: 12293531
    Abstract: A depth sensing system and a depth sensing method are provided. The sensing system includes depth sensing module and a processor for performing the sensing method. The depth sensing method incudes: obtaining a sensed target data set via a depth sensing module; calculating a period number corresponding to a measuring pixel; and calculating an actual range value or an actual depth of the measuring pixel in accordance with a period number and a range value of the measuring pixel. The step of calculating the period number of the target data set includes: calculating a spatial ratio in accordance with the position values of the pixel of optical center and measuring pixel, and a focal length of the depth sensing module; calculating a basic range in accordance with the spatial ratio and an unit depth; and calculating the period number corresponding to the measuring pixel.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: May 6, 2025
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Wu-Feng Chen, Ching-Wen Wang, Cheng Che Tsai, Hsueh-Tsung Lu
  • Patent number: 12292273
    Abstract: The device includes a projecting device, an image sensor and a computing circuit. The projecting device provides a light beam having a predetermined pattern that is projected onto an object. The image sensor receives the light beam reflected from the object to generate an image. The computing circuit compares the image with a first ground-truth image and a ground-truth image to generate a first depth value and a second depth value respectively. The first and second depth values are combined to generate a depth result.
    Type: Grant
    Filed: September 11, 2022
    Date of Patent: May 6, 2025
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Wu-Feng Chen, Ching-Wen Wang, Cheng Che Tsai, Hsueh-Tsung Lu
  • Patent number: 12293985
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20250143031
    Abstract: An electronic device is provided. The electronic device includes a substrate, a driving layer, a semiconductor element, an insulating layer, a first conductive element and a second conductive element. The driving layer is disposed on the substrate and includes a transistor. The semiconductor element is disposed on the driving layer. The insulating layer is disposed between the driving layer and the semiconductor element. The first conductive element passes through the insulating layer to be electrically connected to the semiconductor element. The second conductive element passes through the insulating layer to be electrically connected to the semiconductor element. Moreover, the semiconductor element is electrically connected to the driving layer through the first conductive element and the second conductive element.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Jia-Yuan CHEN, Tsung-Han TSAI, Kuan-Feng LEE
  • Publication number: 20250143037
    Abstract: An electronic device includes a substrate, a circuit layer, a first light emitting unit, a second light emitting unit, and a light conversion layer. The circuit layer is disposed on the substrate. The first and second light emitting units are disposed on the circuit layer and are respectively electrically connected to the circuit layer. The light conversion layer is disposed on the first and second light emitting units and includes a first light conversion unit overlapping the first light emitting unit and a second light conversion unit overlapping the second light emitting unit. The first and second light conversion units correspond to a first color. In a top view, an area of the first light emitting unit is smaller than an area of the second light emitting unit, and an area of the first light conversion unit is the same as an area of the second light conversion unit.
    Type: Application
    Filed: September 26, 2024
    Publication date: May 1, 2025
    Applicant: Innolux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20250134179
    Abstract: An electronic atomization device includes: an atomization apparatus having an atomizer and a power supply body for supplying power to the atomizer, the power supply body having an accommodating cavity for insertion of the atomizer; a charging apparatus configured to be connected to the power supply body so as to charge the power supply body, the charging apparatus comprising an apparatus body and a charging seat, the power supply body being separably supported on the charging seat; and a protective cover coated on the apparatus body and the power supply body.
    Type: Application
    Filed: October 23, 2024
    Publication date: May 1, 2025
    Inventor: Feng CHEN
  • Publication number: 20250142832
    Abstract: A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.
    Type: Application
    Filed: December 29, 2024
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chen Wang, Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang
  • Publication number: 20250136761
    Abstract: The present invention provides a modified bismaleimide prepolymer, a resin composition and application thereof. The modified bismaleimide prepolymer is obtained by a reaction of a bismaleimide compound with an amino organosilicone resin A and an amino organosilicone resin B, where the amino equivalent (EaA) of the amino organosilicone resin A is different from the amino equivalent (EaB) of the amino organosilicone resin B, and the ratio of the total mass of the amino organosilicone resin A and the amino organosilicone resin B to the mass of the bismaleimide compound is (5-80):100. According to the present invention, the reactivity of the bismaleimide compound is improved, and the rheological property of the modified bismaleimide prepolymer applied in the field of substrate materials such as packaging substrates during lamination at high temperature is controlled.
    Type: Application
    Filed: March 31, 2023
    Publication date: May 1, 2025
    Applicants: SHENGYI TECHNOLOGY (SUZHOU) CO., LTD, SHENGYI TECHNOLOGY (CHANGSHU) CO., LTD
    Inventors: Chunmei CUI, Feng JIAO, Hui WANG, Xiangxiu CHEN, Tiekuang DING
  • Publication number: 20250143000
    Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Inventors: MIN-FENG KAO, DUN-NIAN YAUNG, JEN-CHENG LIU, HSING-CHIH LIN, CHE-WEI CHEN