Patents by Inventor Feng Chiang

Feng Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250219583
    Abstract: The present invention provides a power amplifier system configured to receive an input audio signal to generate an output audio signal is disclosed. The power amplifier system includes a reference signal generator, a dynamic headroom generator and a DC-DC converter. The reference signal generator is configured to generate a reference signal according to the input signal. The dynamic headroom generator is configured to generate an output reference signal according to the reference signal and a change rate of a signal, wherein the signal is the reference signal, the input audio signal, or correlated with the reference signal or the input audio signal. The DC-DC converter is configured to generate a supply voltage to a power amplifier, wherein a voltage level of the supply voltage is determined according to the output reference signal, and the power amplifier is configured to generate the output audio signal according to the input audio signal.
    Type: Application
    Filed: December 5, 2024
    Publication date: July 3, 2025
    Applicant: MEDIATEK INC.
    Inventors: Yi-Wei Huang, Yi-Han Pan, Chun-Lung Chang, Sung-Han Wen, Kuan-Hung Chen, Chia-Feng Chiang, Kuan-Ta Chen
  • Patent number: 12285971
    Abstract: An electromagnetic induction hub includes a first disc having a first magnet, a second disc having a second magnet, a coil disc formed between the first disc and the second disc, a bearing penetrates the first disc, the second disc and the coil disc.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: April 29, 2025
    Assignee: Metaone Corporation
    Inventors: Yueh-Feng Chiang, Kuo-Ching Chiang
  • Patent number: 12272687
    Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: April 8, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang
  • Publication number: 20250072941
    Abstract: The present invention relates to a pedicle screw including a nail body, a positioning part and a holding part, wherein the positioning part has a first side and a second side facing the first side, in which the nail body has an end disposed on the first side and the holding part is disposed on the second side. The holding part has left and right ends exhibiting a symmetrical arc shape. Thus, when the spinal fixation surgery is conducted, the holding parts of the two adjacent pedicle screws are stacked on each other, and the cross sectional area occupied by the holding parts on the skin surface is reduced, thereby significantly reducing the corresponding opening width, so that the requirement on minimizing the extent of the wound and minimizing the damage of the soft tissue at the surgical site is satisfied.
    Type: Application
    Filed: August 26, 2024
    Publication date: March 6, 2025
    Inventors: Fon-Yih Tsuang, Chang Che Yang, Yueh-Feng Chiang, Po-Yi Liu
  • Publication number: 20250029940
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 23, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
  • Publication number: 20240413115
    Abstract: A package structure is provided. The package structure includes an electronic component, an encapsulant, a first conductive pillar, a first dielectric layer. The electronic component has an active surface. The encapsulant encapsulates the electronic component and exposes the active surface of the electronic component. The first conductive pillar is over the active surface of the electronic component, wherein an upper surface of the first conductive pillar includes a concave portion. The first dielectric layer is over the encapsulant and the active surface of the electronic component, wherein the first dielectric layer defines an opening exposing the concave portion of the first conductive pillar.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ling YEH, Yuan-Feng CHIANG, Chung-Hung LAI, Chin-Li KAO
  • Publication number: 20240411112
    Abstract: A smart phone includes a lens set formed in front of an image sensor. An optical lens is configurated in front of the lens set, the image sensor or the combination thereof. The optical lens includes at least one transparent layer having trenches, resonators are formed in the trenches, wherein the resonators are formed with different sizes and responsive to different light frequencies.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 12, 2024
    Inventors: Kuo-Ching CHIANG, Yueh-Feng CHIANG
  • Publication number: 20240396374
    Abstract: A wireless charging device includes a wireless communication device configurated in the wireless charging device to communicate with an electric vehicle. At least one transmitting coil is connected to a power supply to wirelessly charge the electric vehicle, and at least one resonant coil is configurated in front of the at least one transmitting coil to form a negative or zero refractive index medium by resonance.
    Type: Application
    Filed: May 22, 2024
    Publication date: November 28, 2024
    Inventors: Kuo-Ching CHIANG, Yueh-Feng CHIANG
  • Patent number: 12107056
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 1, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang, Po-Wei Lu
  • Publication number: 20240243527
    Abstract: A connecting structure includes a flexible flat cable. The flexible flat cable includes a first end portion, a second end portion, a connecting portion, a first pad region, a second pad region and a slot. The connecting portion is connected between the first end portion and the second end portion. The first pad region is disposed on the first end portion. The second pad region is disposed on the second end portion. The slot is formed in the connecting portion. The slot is extended along a length direction of the flexible flat cable. The flexible flat cable is a laminated structure including at least one set of signal trace pattern and at least one shielding structure. The at least one shielding structure correspondingly surrounds the at least one set of signal trace pattern in the connecting portion.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 18, 2024
    Applicant: CYNTEC CO., LTD.
    Inventors: Shih-Hsien Tseng, Sheng-Ju Chou, Ming-Feng Chiang
  • Publication number: 20240128206
    Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Peng YANG, Yuan-Feng CHIANG, Po-Wei LU
  • Publication number: 20240126018
    Abstract: The present disclosure provides an optical device including a tray with a step structure, first filters, second filters, and an optical signal router. The step structure has a first portion and a second portion laterally connected to the first portion. The first portion has a first bottom surface and a first top surface. The second portion has a second bottom surface and a second top surface. The first bottom surface and the second bottom surface are substantially coplanar, and the first portion is thinner than the second portion. The first filters are mounted on the first top surface. The second filters are mounted on the second top surface. The optical signal router optically couples to the first filters and the second filters, and is configured to receive a light beam, transmissible to the tray, from one of the first filters or the second filters.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: FENG-CHIANG CHAO, CHANG-YI PENG
  • Patent number: 11837557
    Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 5, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Peng Yang, Yuan-Feng Chiang, Po-Wei Lu
  • Patent number: 11791227
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
  • Publication number: 20230153505
    Abstract: Electronic design automation (EDA) of the present disclosure logically places components of the electronic circuitry onto an electronic design real estate to determine an architectural design placement for the electronic circuitry. The EDA evaluates a metaheuristic algorithm starting with an initial placement of components of the electronic circuitry onto the electronic design real estate to provide multiple possible placements for placing these components of the electronic circuitry onto the electronic design real estate. The EDA utilizes the multiple possible placements of the metaheuristic algorithm to train one or more probabilistic functions of a model-based reinforcement learning (RL) algorithm. The EDA evaluates the model-based RL algorithm utilizing the one or more probabilistic functions to determine the architectural design placement.
    Type: Application
    Filed: September 6, 2022
    Publication date: May 18, 2023
    Applicant: MediaTek Inc.
    Inventors: Wei-Hao CHANG, Kai-En YANG, Kao-I CHAO, Yu-Hsun CHEN, Cheng-Feng CHIANG, Yen Min TSAI, Sau Loong LOW, Chia-Shun YEH, Bun Suan HENG, Chia-Yu TSAI, Chin-Tang LAI, Hung-Hao SHEN
  • Publication number: 20230094668
    Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.
    Type: Application
    Filed: December 6, 2022
    Publication date: March 30, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Yuan-Feng CHIANG
  • Publication number: 20230055030
    Abstract: A basic structural body for constructing heat dissipation device and a heat dissipation device are disclosed. The heat dissipation device includes a first basic structural body having a wick structure formed on one side surface thereof; and the first basic structural body and the wick structure are structural bodies formed layer by layer. Two pieces of first basic structural bodies can be correspondingly closed together to construct a heat dissipation device internally defining an airtight chamber. In this manner, the heat dissipation device can be designed in a more flexible manner.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 23, 2023
    Inventor: Kuei-Feng Chiang
  • Publication number: 20220412666
    Abstract: A basic structural body for constructing heat dissipation device and a heat dissipation device are disclosed. The heat dissipation device includes a first basic structural body having a wick structure formed on one side surface thereof; and the first basic structural body and the wick structure are structural bodies formed layer by layer. Two pieces of first basic structural bodies can be correspondingly closed together to construct a heat dissipation device internally defining an airtight chamber. In this manner, the heat dissipation device can be designed in a more flexible manner.
    Type: Application
    Filed: August 28, 2022
    Publication date: December 29, 2022
    Inventor: Kuei-Feng Chiang
  • Patent number: 11521958
    Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang
  • Patent number: 11520452
    Abstract: The present invention discloses a noise reduction touch light adjustment device including a light adjustment film, a capacitive touch panel, a noise reduction film, a glass substrate, a control circuit module, and an alternating current (AC) transformer. The noise reduction film is disposed between the light adjustment film and the capacitive touch panel to lower noise inputted from the AC transformer into the light adjustment film such that the capacitive touch panel is ensured to be operated precisely.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 6, 2022
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Yi-Feng Chiang, Cheng-Yi Huang