Abstract: A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: A method for fabricating an image sensor device is provided. The method includes forming a plurality of photosensitive pixels in a substrate; depositing a dielectric layer over the substrate; etching the dielectric layer, resulting in a first trench in the dielectric layer and laterally surrounding the photosensitive pixels; and forming a light blocking structure in the first trench, such that the light blocking structure laterally surrounds the photosensitive pixels.

Abstract: A pixel array may include air gap reflection structures under a photodiode of a pixel sensor to reflect photons that would otherwise partially refract or scatter through a bottom surface of a photodiode. The air gap reflection structures may reflect photons upward toward the photodiode so that the photons may be absorbed by the photodiode. This may increase the quantity of photons absorbed by the photodiode, which may increase the quantum efficiency of the pixel sensor and the pixel array.

Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: In some implementations, a pixel array may include a near infrared (NIR) cut filter layer for visible light pixel sensors of the pixel array. The NIR cut filter layer is included in the pixel array to absorb or reflect NIR light for the visible light pixel sensors to reduce the amount of MR light absorbed by the visible light pixel sensors. This increases the accuracy of the color information provided by the visible light pixel sensors, which can be used to produce more accurate images. In some implementations, the visible light pixel sensors and/or MR pixel sensors may include high absorption regions to adjust the orientation of the angle of refraction for the visible light pixel sensors and/or the MR pixel sensors, which may increase the quantum efficiency of the visible light pixel sensors and/or the MR pixel sensors.

Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Abstract: A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.

Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.

Abstract: An image sensor device includes a substrate, photosensitive pixels, an interconnect structure, a dielectric layer, and a light blocking element. The photosensitive pixels are in the substrate. The interconnect structure is over a first side of the substrate. The dielectric layer is over a second side of the substrate opposite the first side of the substrate. The light blocking element has a first portion extending over a top surface of the dielectric layer and a second portion extending in the dielectric layer. The second portion of the light blocking element laterally surrounds the photosensitive pixels.

Abstract: A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.

Abstract: A pixel sensor may include a deep trench isolation (DTI) structure that extends the full height of a substrate in which a photodiode of the pixel sensor is included. Incident light entering the pixel sensor at a non-orthogonal angle is absorbed or reflected by the DTI structure along the full height of the substrate. In this way, the DTI structure may reduce, minimize, and/or prevent the incident light from traveling through the pixel sensor and into an adjacent pixel sensor along the full height of the substrate. This may increase the spatial resolution of an image sensor in which the DTI structure is included, may increase the overall sensitivity of the image sensor, may reduce and/or prevent color mixing between pixel sensors of the image sensor, and/or may decrease image noise after color correction.

Abstract: A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips.

Abstract: A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips.

Abstract: A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.

Abstract: The present disclosure describes an image sensor device and a method for forming the same. The image sensor device can include a semiconductor layer. The semiconductor layer can include a first surface and a second surface. The image sensor device can further include an interconnect structure formed over the first surface of the semiconductor layer, first and second radiation sensing regions formed in the second surface of the semiconductor layer, a metal stack formed over the second radiation sensing region, and a passivation layer formed through the metal stack and over a top surface of the first radiation sensing region. The metal stack can be between the passivation layer and an other top surface of the second radiation sensing region.

Abstract: A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Abstract: A pixel array includes a plurality of dark pixel sensors configured to generate dark current calibration information for a plurality of visible light pixel sensors included in the pixel array. The plurality of dark pixel sensors may generate respective dark current measurements for each of the plurality of visible light pixel sensors or for small subsets of the plurality of visible light pixel sensors. In this way, each of the plurality of visible light pixel sensors may be individually calibrated (or small subsets of the plurality of visible light pixel sensors may be individually calibrated) based on an estimated dark current experienced by each of the plurality of visible light pixel sensors. This may enable more accurate dark current calibration of the visible light pixel sensors included in the pixel array, and may be used to account for large differences in estimated dark currents for the visible light pixel sensors.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.