Abstract: A three-dimensional (3D) memory device comprising a 3D memory array, an encoding circuit, a sensing circuit and a processing circuit is provided in present disclosure. The 3D memory array comprises multiple two-dimensional (2D) memory arrays and is configured to receive multiple input voltages and output multiple output currents. Each 2D memory array comprises multiple memory cells and a four-array-side edge. The encoding circuit and the sensing circuit are coupled to the processing circuit and the four-array-side edge, and respectively configured to input the input voltages and receive the output currents. The processing circuit is configured to perform an in-memory-computing according to the input voltages and the output currents. The four-array-side edge has multiple array sides. When one of the array sides is configured to receive the input voltages, another is configured to output the output currents, wherein the one of the array sides is not parallel to the another.

Abstract: A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.

Abstract: A manufacturing method of a memory device is disclosed herein. The manufacturing method includes: arranging first layers and second layers alternatively along a first direction; etching the first layers and the second layers to form a first hole extending along the first direction; forming a first channel structure at an edge of the first hole; forming a first source structure and a first drain structure inside the first hole; and forming a first charge trap structure surrounding the first channel structure, in which a material of the first layers is different from a material of the second layers.

Abstract: A memory device includes a first memory cell including channel, source and drain structures and a charge trap layer. When a first data bit has a first logic value and a voltage signal applied to the charge trap layer has a first voltage level, a current signal flowing through the channel structure has a first current level. When the first data bit has the first logic value and the voltage signal has a second voltage level, the current signal has a second current level. When the first data bit has a second logic value and the voltage signal has the first voltage level, the current signal has the second current level. When the first data bit has the second logic value and the voltage signal has the second voltage level, the current signal has the first current level.

Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

Abstract: An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

Abstract: A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

Abstract: A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.

Abstract: An integrated circuit structure includes a substrate, an interconnect stack, a first memory array, and a source line. The interconnect stack is over the substrate. The first memory array is over the interconnect stack and includes memory elements stacked in a vertical direction each comprising a conductive layer. The first memory array further includes a memory layer electrically connecting to the conductive layers of the memory elements and extending downwardly from a topmost one of the conductive layers to a lowermost one of the conductive layers; and a channel layer extending along a sidewall of the memory layer. The source line is in contact with a top end of the channel layer and laterally extends across the first memory array.

Abstract: A memory device includes a first memory cell, a first switch element and a second switch element. The first memory cell is configured to store a first data bit, and configured to perform a search operation to the first data bit by a first search bit to generate a first current signal. The first switch element is coupled in series with the first memory cell, and configured to be turned on in response to a clamp voltage level during the search operation, to clamp the first current signal. The second switch element is coupled in series with the first memory cell, and configured to be turned on in response to a first enable voltage level. The first enable voltage level is larger than the clamp voltage level.

Abstract: The integrated circuit structure includes a substrate and a first resistive memory string over the substrate. The first resistive memory string includes memory cells, and each of the memory cells includes a word line transistor and a resistor. The word line transistor includes a channel region, a gate over the channel region, and a plurality of source/drain regions on opposite sides of the channel region. The resistor is over the word line transistor and is connected with the word line transistor in parallel. The word line transistors of two adjacent memory cells share a same one of the source/drain regions, and the memory cells are connected in series using the sharing ones of the source/drain regions.

Abstract: A TCAM comprises multiple first search lines, multiple second search lines, multiple memory cell strings, and one or more current sensing units coupled to the plurality of memory cell strings. Each memory cell string comprises multiple memory cells. Each memory cell string comprises at least four transistors serially connected as a NAND memory string, and two transistors of the at least four transistors form each memory cell. One, of the two transistors in each memory cell, coupled to one of the first search lines is a first transistor, and the other one, of the two transistors in each memory cell, coupled to one of the second search lines is a second transistor. The multiple first search lines are arranged consecutively, and the multiple second search lines are arranged consecutively.

Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

Abstract: A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.

Abstract: A memory device includes a first memory cell performing a logic operation. The first memory cell includes first and second switches. The first switch writes a first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and a first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.

Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.