Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

Abstract: A multiplication and addition operation device and a control method thereof are provided. The multiplication and addition operation device includes a feature information filter and an in-memory calculator. The feature information filter records a plurality of designated bits of a plurality of feature information, compares received input information with the designated bits to generate a comparison result, and generates a selected address according to the comparison result. The in-memory calculator records all bits of the feature information, and generates an operation result by performing a multiplication and addition operation on the feature information and the input information according to the selected address.

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

Abstract: A data recognition apparatus and a recognition method are provided. The data recognition apparatus includes a data augmentation device, a feature extractor, and a comparator. The data augmentation device receives a plurality of target information and performs augmentation on each of the target information to generate a plurality of augmented target information. The feature extractor receives queried information and the augmented target information to extract features of the augmented target information and the queried information to respectively generate a plurality of augmented target feature values and a queried feature value. The comparator generates a recognition result according to the queried feature value and the augmented target feature values.

Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.

Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Abstract: Memory devices based on tungsten oxide memory elements are described, along with methods for manufacturing such devices. A memory device includes a plug extending upwardly from a top surface of a substrate through a dielectric layer; a bottom electrode having tungsten on an outside surface, the bottom electrode extending upwardly from a top surface of the plug; an insulating material in contact with the tungsten on the outside surface of, and surrounding, the bottom electrode; a memory element on an upper surface of the bottom electrode, the memory element comprising a tungsten oxide compound and programmable to at least two resistance states; and a top electrode overlying and contacting the memory element. The plug has a first lateral dimension, and the bottom electrode has a lateral dimension parallel with the first lateral dimension of the plug that is less than the first lateral dimension.

Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable threshold transistors in the array with thresholds corresponding to values of a weight factor Wmn for the corresponding cell. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

Abstract: A method for accelerating a convolution of a kernel matrix over an input matrix for computation of an output matrix using in-memory computation involves storing in different sets of cells, in an array of cells, respective combinations of elements of the kernel matrix or of multiple kernel matrices. To perform the convolution, a sequence of input vectors from an input matrix is applied to the array. Each of the input vectors is applied to the different sets of cells in parallel for computation during the same time interval. The outputs from each of the different sets of cells generated in response to each input vector are sensed to produce a set of data representing the contributions of that input vector to multiple elements of an output matrix. The sets of data generated across the input matrix are used to produce the output matrix.

Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each including a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable resistors in the array with resistances corresponding to values of a weight factor Wmn for the corresponding cell. Alternatively, the resistances can be programmed during manufacture. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

Abstract: A non-volatile memory and its reading method are provided. The reading method includes: erasing a plurality of memory cells in a memory cell string; setting a target memory cell of the memory cells, setting an initial voltage, generating a plurality of programming voltages by gradually increasing the initial voltage based on a step value, sequentially performing a plurality of programming operations by the target memory cell according to the programming voltages, and verifying the target memory cell to obtain a first verifying current during the programming operations; setting a corresponding programming voltage as a target voltage through determining the first verifying current and a first reference current; and performing the programming operations on the memory cells other than the target memory cell according to the target voltage and setting the memory cell string as a reading reference memory cell string.

Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programming/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.

Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.

Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.