Abstract: A method for forming a metal liner layer for an interconnect uses a multi-metal deposition process to produce a reduced thickness liner. The back-end-of-the-line packaging process may include forming a metal liner layer by depositing a ruthenium layer with a first thickness of approximately 5 angstroms or less and depositing a first cobalt layer with a second thickness of approximately 20 angstroms or less. In some embodiments, the ruthenium layer may be deposited on a previously formed barrier layer and then undergoes a treatment process before depositing the first cobalt layer. In some embodiments, the first cobalt layer may be deposited on the ruthenium layer or the ruthenium layer maybe deposited on the first cobalt layer. In some embodiments, the ruthenium layer is deposited on the first cobalt layer and a second cobalt layer is deposited on the ruthenium layer.

Abstract: The present disclosure provides an antenna, a method for manufacturing an antenna and a communication system. The antenna includes: a dielectric layer; a first electrode having at least one first opening therein; at least one radiating structure on a side of the dielectric layer different from that with the first electrode thereon; an orthographic projection of the radiating structure on the dielectric layer is located in that of the first opening on the dielectric layer; each radiating structure includes a second electrode and a third electrode, orthographic projections of the second and third electrodes on the dielectric layer are located in that of the first opening on the dielectric layer, the orthographic projections of the second and third electrodes on the dielectric layer are not overlapped; at least one first feed line and at least one second feed line.

Abstract: A display substrate includes a base substrate, a voltage line arranged at a peripheral region of the base substrate, an encapsulation layer arranged at a side of the voltage line away from the base substrate, and a plurality of pixel units arranged at a display region of the base substrate. The encapsulation layer is arranged at a part of the display region and the peripheral region of the base substrate. The display substrate further includes an antenna arranged at a side of the encapsulation layer away from the base substrate, the antenna is a grid-like antenna, the voltage line is provided with a hollowed-out portion, and an orthogonal projection of at least a part of an end of the antenna onto the base substrate is located within an orthogonal projection of the hollowed-out portion onto the base substrate.

Abstract: An array substrate, an opposite substrate and a display panel are provided. The array substrate comprises: a display region and a periphery region surrounding the display region, wherein the display region comprises a plurality of pixel regions, and each of the pixel regions comprises a reflective region and a transmissive region; the reflective region comprises a driving signal outputting layer, a segment gap layer, a passivation layer and a reflective layer, the reflective layer is coupled to the driving signal outputting layer to enable both the reflective layer and the driving signal outputting layer to function as a reflective region driving electrode; the transmissive region comprises a first electrode layer, the first electrode layer is coupled to the driving signal outputting layer, the passivation layer extends to the transmissive region, and the passivation layer is arranged between the first electrode layer and a first base of the display substrate.

Abstract: An antenna includes: a dielectric layer having first and second surfaces opposite to each other; a radiating layer on the first surface, and having therein a slit; a first shielding layer on the second surface, and being electrically connected to the radiating layer; a first insulating layer on an upper side of the radiating layer; and a switch unit on an upper side of the first insulating layer, and corresponding to the slit. Each switch unit includes: a first electrode, a second insulating layer, a connecting portion, and a second electrode on the first insulating layer sequentially. Orthogonal projections of the first and second electrodes on the dielectric layer overlap each other. The connecting portion is connected to the second electrode to form a gap between the first and second electrodes. Orthogonal projections of the second electrode and a corresponding slit on the dielectric layer overlap each other.

Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.

Abstract: A set of primers and probes for simultaneous detection of Cymbidium mosaic virus (CymMV), Odontoglossum ringspot virus (ORSV), and Cymbidium ringspot virus (CymRSV) and a method for detecting CymMV, ORSV, and CymRSV, along with a method for their detection, are disclosed. The method involves designing multiplex real-time quantitative PCR detection primers and probes for CymMV, ORSV, and CymRSV and applying these primers and probes to the real-time quantitative PCR simultaneous detection of CymMV, ORSV, and CymRSV. It allows for faster detection of CymMV, ORSV, and CymRSV, taking only one-third of the time compared to uniplex real-time quantitative PCR technology, thereby reducing testing costs by approximately ? to ½ for each sample. The primers and probes are highly specific and sensitive, with a sensitivity as low as 1 to 10 copies. It provides an efficient and feasible detection method for early detection and prevention of CymMV, ORSV, and CymRSV.

Abstract: A silicon-based solid amine sorbent for CO2 and the making method thereof including: providing a silicon source liquid which is a silicate solution or a liquid organosilicate, wherein the silicate solution comprises water and a first silicate dissolved in the water; mixing the silicon source liquid with a precipitant to perform a precipitation reaction to obtain a product liquid containing a precipitate, wherein the precipitate is a second silicate or silicic acid; filtering out the precipitate and washing the precipitate with water; mixing the precipitate filtrated out but not dried yet with an organic alcohol and then performing an azeotropic distillation to obtain a dehydrated precipitate; calcining the dehydrated precipitate to obtain a silicon-based support, wherein the silicon-based support is a powder of the second silicate powder or a silica powder; and impregnating the silicon-based support with an organic amine solution and then drying to obtain the silicon-based amine-containing solid sorbent for C

Abstract: The present disclosure relates to an array substrate. At least one of a pixel electrode and a common electrode in the array substrate has an electrode structure. The electrode structure includes: first and second electrode portions, and a conductive connection portion. The first electrode portion includes a first connection bar and first electrode bars. The second electrode portion includes a second connection bar and second electrode bars. No common line is provided in each of the sub-pixel regions.

Abstract: Embodiments of this application provide a display panel and a manufacturing method thereof, and a terminal device, which are applied to the field of terminal technologies. The display panel includes a rigid substrate, a driving circuit layer arranged on the rigid substrate, and a first organic layer structure, a conductive layer and a second organic layer structure that are sequentially arranged away from the rigid substrate, where the rigid substrate and the driving circuit layer are arranged bypassing a bendable region, and first organic layer structure, the conductive layer, and the second organic layer structure are distributed in at least a first peripheral region, the bendable region, and a binding region.

Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an NV region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 ?m and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×1011/cm3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.

Abstract: An array substrate has a display area and a non-display area including a first bonding region. The array substrate includes: a plurality of pixel columns disposed in the display area, each of the plurality of pixel columns including a plurality of light-emitting units that are arranged in a second direction, the second direction being perpendicular to a direction in which an edge of the display area proximate to the first bonding region extends; and at least three first power supply input terminals disposed in the first bonding region, each first power supply input terminal being connected to at least one pixel column of the plurality of pixel columns, so as to provide a first power supply signal to the at least one pixel column.

Abstract: A material conveying device includes a base frame, a first conveying unit, a second conveying unit and a transfer assembly. The first conveying unit is provided on the base frame, the second conveying unit is provided on the base frame, and the transfer assembly is provided on the base frame and can transfer a material between the first conveying unit and the second conveying unit. The present disclosure further provides a processing equipment facilitating material distribution and a material distribution method.

Abstract: An array substrate includes a base substrate including a first surface and a second surface, scanning signal lines disposed on the first surface, at least two groups of shift register circuits disposed in a display area of the first surface, and at least one fan-out structure disposed on the second surface. Each scanning signal line extends along a first direction. Each group of shift register circuits includes a plurality of shift register circuits along a second direction. Each shift register circuit is coupled to a scanning signal line. The fan-out structure is coupled to the shift register circuits. At least one group of shift register circuits is disposed in a non-edge region of the display area. The shift register circuit disposed in the non-edge region is configured to transmit a scanning signal to the scanning signal line at both sides of the shift register circuit along the first direction.

Abstract: The present disclosure provides a thin film sensor and a manufacturing method thereof, and belongs to the technical field of sensors. The thin film sensor of the present disclosure has a plurality of conductive-wire regions intersecting each other, and a plurality of hollow-out parts defined by the plurality of conductive-wire regions; the thin film sensor includes: a base substrate; a plurality of conductive wires on the base substrate, with the conductive wires being in the conductive-wire regions one to one; and a functional structure on the base substrate, where the functional structure is configured to allow at least part of light, which is transmitted along a preset direction and enters the functional structure from the conductive wire-regions, to exit from the hollow-out parts, and the preset direction is a direction from the base substrate towards the conductive wires.

Abstract: Disclosed is a display panel including: first spacer on the array substrate, an orthographic projection of the first spacer on the array substrate being a first pattern extending along a first direction; a second spacer on the counter substrate, an orthographic projection of the second spacer on the array substrate being a second pattern extending along a second direction; at least two third spacers, orthographic projections of which on the array substrate being respectively on two sides of the first pattern along the first direction; at least two fourth spacers, orthographic projections of which on the array substrate being respectively on two sides of the second pattern along the second direction; one of the third spacer and the fourth spacer is on the array substrate, and the other is on the counter substrate.

Abstract: The disclosure provides a display panel and a display apparatus, and belongs to the field of display technology. The display panel includes a display backplane and an antenna structure; the display panel further includes a frequency selective surface on a side of the antenna structure close to a light exit surface of the display panel; the frequency selective surface is configured to transmit an electromagnetic wave with a specific frequency, so as to enhance a radiation gain of the antenna structure.

Abstract: The present disclosure provides an antenna device and a manufacturing method therefor, a control method, and an electronic device. The antenna device includes a first and a second substrate structure, and a liquid crystal layer between the first and the second substrate structure. The first substrate structure includes a first substrate and multiple antenna patches. The second substrate structure is on the side of the multiple antenna patches away from the first substrate, and includes a second substrate and a metal layer having multiple gaps. One gap corresponds to one antenna patch, the region where the orthographic projection of each gap on the first substrate overlaps that of the corresponding antenna patch is a first region, the orthographic projection of each gap on the first substrate further includes a second region and a third region, and the third region is located between the second region and the third region.

Abstract: An antenna and an antenna system. The antenna includes: a first dielectric layer (1) having a first surface and a second surface, which are arranged opposite each other in a thickness direction thereof; a radiation patch (2), which is arranged on the first surface of the first dielectric layer; and a first electrode layer (3), which is arranged on the second surface of the first dielectric layer, and at least partially overlaps with the orthographic projection of the radiation patch on the second surface, wherein the first electrode layer has inner recesses (31, 32), and openings of the inner recesses face the radiation patch. The orthographic projection of at least part of a radiation edge of the radiation patch on the first dielectric layer at least partially overlaps with the orthographic projections of the inner recesses on the first surface.