Abstract: The present disclosure provides a phase shifter and an antenna. The phase shifter includes: a substrate; a signal electrode, and a first reference electrode and a second reference electrode respectively on two sides of an extending direction of the signal electrode; an interlayer insulating layer on the signal electrode, the first reference electrode and the second reference electrode; and at least one phase control unit each including a film bridge. At least part of the at least one phase control unit further includes at least one driving structure including at least a driving electrode; at least part of the at least one driving structure has a different height from a height of the signal electrode in a direction away from the substrate; the driving structure in each phase control unit is at least partially overlapped an orthographic projection of the film bridge on the substrate.

Abstract: A mesh structure is provided. The mesh structure includes a first insulating layer; one or more mesh lines on a first side of the first insulating layer; and one or more protruding structures on a second side of the first insulating layer, the second side being opposite to the first side. An orthographic projection of a respective protruding structure on a projection plane containing a surface of the first insulating layer at least partially overlaps with an orthographic projection of a respective mesh line on the projection plane. A refractive index of the one or more protruding structures is greater than a refractive index of the first insulating layer.

Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1?k?K?N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n?i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2. K=12, the input signal terminal of the n-th stage is connected to an output signal terminal of a (n?6)-th stage, and the reset signal terminals of the n-th stage and the (n+1)-th stage are connected to an output signal terminal of a (n+8)-th stage or a (n+10) stage.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a gate driving circuitry arranged at a peripheral region of the display substrate; n clock signal leads coupled to the gate driving circuitry, each clock signal lead extending in a first direction; and n clock signal lines arranged sequentially in the first direction, each clock signal line extending in a second direction intersecting the first direction, where n is a positive integer greater than 1. The clock signal leads have a same length in the first direction, each clock signal lead extends from a first clock signal line to an nth clock signal line, and each clock signal lead is coupled to a corresponding clock signal line at a position where the clock signal lead intersects the clock signal line.

Abstract: An array antenna module is provided, which includes a feed structure, a phase shift structure, and a radiation structure. The feed structure is connected to the phase shift structure, and the phase shift structure is connected to the radiation structure. The feed structure, the phase shift structure, and the radiation structure are all disposed on a glass substrate.

Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.

Abstract: Provided are a phase shifter, a driving method therefor and an antenna. The phase shifter includes a first substrate and a second substrate, which are disposed opposite to each other, and a first dielectric layer disposed therebetween; the first substrate includes: a first base, and a first reference electrode layer disposed on a side of the first base close to the first dielectric layer, and including first reference electrodes insulated and spaced apart from one another and each having a first opening; the second substrate includes a second base, first transmission lines on the second base and spaced apart from one another; the first transmission lines are in one-to-one correspondence with the first reference electrodes; an orthographic projection of a first transmission end of each first transmission line on the second base at least partially overlaps that of the first opening corresponding thereto on the second base.

Abstract: An antenna unit includes: a first substrate, a second substrate, and a third substrate which are stacked. The second substrate has a first slotted area. A liquid crystal layer is arranged in a cavity formed by the first substrate, the first slotted area of the second substrate, and the third substrate. The first substrate includes: a first base substrate, a ground layer on one side of the first base substrate close to the second substrate, and a feed structure layer on one side of the first base substrate away from the second substrate. Orthogonal projections of the ground layer and the feed structure layer on second substrate overlap with an orthogonal projection of first slotted area on the second substrate. The third substrate includes: a third base substrate, and a radiation structure layer on one side of the third base substrate close to the second substrate.

Abstract: An antenna structure includes a first substrate and a second substrate. There is a dielectric layer between the first substrate and the second substrate. The first substrate includes a first dielectric substrate, and a radiation patch and a micro-strip arranged on the first dielectric substrate. The radiation patch and the micro-strip are on one side of the first dielectric substrate away from the second substrate. Orthographic projections of the micro-strip and the radiation patch on the first dielectric substrate do not overlap. The radiation patch has at least one first slot away from the micro-strip. The second substrate includes a second dielectric substrate, a feed structure arranged on one side of the second dielectric substrate close to the first substrate, and a ground layer arranged on one side of the second dielectric substrate away from the first substrate. The feed structure is electrically connected to the micro-strip.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes p pixel unit groups, and each of the p pixel unit groups includes q rows of pixel units, both p and q being integers greater than or equal to 2. Pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register, and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively.

Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1?k?K?N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n?i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2.

Abstract: An antenna structure includes a dielectric substrate, a ground layer and a radiation layer located at two opposite sides of the dielectric substrate. The ground layer has two first gaps which are symmetrical about a central axis of the antenna structure in a first direction to introduce a radiation zero. The radiation layer has two second gaps which are symmetrical about the central axis, edges of the two second gaps are aligned with edges of the radiation layer in a second direction to introduce another radiation zero. The second direction is perpendicular to the first direction.

Abstract: A slot antenna and a communication device including the slot antenna are provided. The slot antenna includes: a dielectric layer having a first surface and a second surface opposite to each other, a radiation layer on the first surface of the dielectric layer and having a plurality of slots therein, and a first shielding layer on the second surface of the dielectric layer and electrically connected to the radiation layer.

Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.

Abstract: A MEMS phase shifter, including: a substrate; a coplanar waveguide signal structure on the substrate; two coplanar waveguide ground wires respectively at two sides of the coplanar waveguide signal structure; insulating isolation layers respectively on the two coplanar waveguide ground wires; and a metal film bridge across and over the coplanar waveguide signal structure and forming a gap with the coplanar waveguide signal structure, both ends of the metal film bridge respectively attached to the insulating isolation layers on the two coplanar waveguide ground wires, wherein an insulating dielectric layer is provided on the coplanar waveguide signal structure, and the insulating dielectric layer comprises at least one concave part, which is concave in the direction towards the substrate, on the surface facing the metal film bridge.

Abstract: Disclosed are a display substrate, a display panel and a display device. The display substrate has a display region and a non-display region, wherein the display substrate includes a base substrate; a near-field communication antenna on the base substrate and comprising a main body, wherein the main body is in the display region, and at least a portion of the main body is transparent.

Abstract: The present disclosure provides a radio frequency duplexer circuit and a radio frequency substrate. The radio frequency duplexer circuit includes a first terminal, a second terminal, a third terminal, a low-pass filter, and a high-pass filter. The low-pass filter includes N first filter sub-circuits coupled in series and a first tuning sub-circuit. Among the N first filter sub-circuits coupled in series, a first end of a 1st first filter sub-circuit is coupled to the first terminal, and a second end of a Nth first filter sub-circuit is coupled to the second terminal. The high-pass filter includes M second filter sub-circuits coupled in series and a second tuning sub-circuit. Among the M second filter sub-circuits coupled in series, a first end of a 1st second filter sub-circuit is coupled to the first terminal, and a second end of a Mth second filter sub-circuit is coupled to the third terminal.

Abstract: A display device includes a backlight module; a display module located on a light exiting side of the backlight module; and a housing accommodating the backlight module and the display module. The display module includes a display panel including an array substrate and a color film substrate arranged opposite to each other. The color film substrate is located between the array substrate and the backlight module. A first polarizer located on one side of the array substrate away from the color film substrate. A manufacturing method of a display device is also provided.

Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.

Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.