Patents by Inventor Feng Qu
Feng Qu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220084451Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.Type: ApplicationFiled: June 8, 2021Publication date: March 17, 2022Inventors: Zhihua Sun, Yinlong Zhang, Qiujie Su, Feng Qu, Jing Liu, Yanping Liao, Xibin Shao
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Patent number: 11239198Abstract: A chip bonding method and a bonding device. The chip bonding method is used for bonding a chip to a display module, the display module includes a substrate and a functional layer on the substrate, the substrate includes a first substrate portion and a second substrate portion, the functional layer is on the first substrate portion, and an electrode is on an upper side of the second substrate portion. The chip bonding method includes: forming a light absorbing film layer on a side of the second substrate portion facing away from the electrode; coating a conductive adhesive film on the electrode, and placing the chip on the conductive adhesive film; and irradiating, by using a laser beam, a side of the second substrate portion facing away from the electrode.Type: GrantFiled: March 26, 2020Date of Patent: February 1, 2022Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lili Wang, Haiwei Sun, Zhenxing Tang, Feng Qu, Jing Liu, Chao Liu, Chuhang Wang, Qiangwei Cui, Ke Meng, Linhui Gong
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Publication number: 20210408692Abstract: A slot antenna and a communication device including the slot antenna are provided. The slot antenna includes: a dielectric layer having a first surface and a second surface opposite to each other, a radiation layer on the first surface of the dielectric layer and having a plurality of slots therein, and a first shielding layer on the second surface of the dielectric layer and electrically connected to the radiation layer.Type: ApplicationFiled: June 28, 2021Publication date: December 30, 2021Inventors: Jia FANG, Feng QU
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Publication number: 20210167094Abstract: An array substrate includes a base substrate including a first surface, a plurality of scanning signal lines disposed on the first surface, and at least two groups of shift register circuits disposed in a display area of the first surface. The first surface has the display area. Each scanning signal line extends along a first direction. Each group of shift register circuits includes a plurality of shift register circuits arranged along a second direction. Each shift register circuit is coupled to a scanning signal line. The first direction and the second direction intersect. At least one group of shift register circuits is disposed in a non-edge region of the display area. The shift register circuit disposed in the non-edge region of the display area is configured to transmit a scanning signal to the scanning signal line at both sides of the shift register circuit along the first direction.Type: ApplicationFiled: November 29, 2019Publication date: June 3, 2021Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Dongni LIU, Minghua XUAN, Feng QU, Qi QI
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Publication number: 20210159208Abstract: A chip bonding method and a bonding device. The chip bonding method is used for bonding a chip to a display module, the display module includes a substrate and a functional layer on the substrate, the substrate includes a first substrate portion and a second substrate portion, the functional layer is on the first substrate portion, and an electrode is on an upper side of the second substrate portion. The chip bonding method includes: forming a light absorbing film layer on a side of the second substrate portion facing away from the electrode; coating a conductive adhesive film on the electrode, and placing the chip on the conductive adhesive film; and irradiating, by using a laser beam, a side of the second substrate portion facing away from the electrode.Type: ApplicationFiled: March 26, 2020Publication date: May 27, 2021Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lili WANG, Haiwei SUN, Zhenxing TANG, Feng QU, Jing LIU, Chao LIU, Chuhang WANG, Qiangwei CUI, Ke MENG, Linhui GONG
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Publication number: 20210062366Abstract: A method for heat-treating a silicon single crystal wafer to control a BMD density thereof to achieve a predetermined BMD density by performing an RTA heat treatment on a silicon single crystal wafer composed of an Nv region in a nitriding atmosphere, and then performing a second heat treatment, the method including: formulating a relational equation for a relation between BMD density and RTA temperature in advance; and determining an RTA temperature for achieving the predetermined BMD density according to the relational equation. Consequently, a method for heat-treating a silicon single crystal wafer for manufacturing an annealed wafer or an epitaxial wafer each having defect-free surface and a predetermined BMD density in a bulk portion thereof.Type: ApplicationFiled: December 25, 2018Publication date: March 4, 2021Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng QU, Ken SUNAKAWA, Tadashi NAKASUGI
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Publication number: 20170253995Abstract: A method for heat-treating a silicon single crystal wafer by an RTA treatment, including: putting a silicon single crystal wafer having an Nv region for the entire plane of the silicon single crystal wafer or an Nv region containing an OSF region for the silicon single crystal wafer entire plane into an RTA furnace, performing pre-heating at temperature lower than temperature at which silicon reacts with NH3 while supplying gas that contains NH3 into the RTA furnace, subsequently stopping the supply of the gas containing NH3 and starting supply of Ar gas to start an RTA treatment under Ar gas atmosphere in which the NH3 gas remains. This provide a method for heat-treating a silicon single crystal wafer that give gettering capability without degrading TDDB properties even to a silicon single crystal wafer in which the entire plane is an Nv region or an Nv region containing an OSF region.Type: ApplicationFiled: September 17, 2015Publication date: September 7, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng QU, Fumio TAHARA, Masahiro SAKURADA, Shuji TAKAHASHI
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Patent number: 9708726Abstract: A silicon wafer heat treatment method includes: placing a silicon wafer on a SiC jig and into a heat treatment furnace; performing heat treatment on the silicon wafer in the heat treatment furnace in a first non-oxidizing atmosphere; reducing the temperature; and carrying the silicon wafer out of the heat treatment furnace. In the heat reduction step, after the temperature is reduced to the temperature at which the silicon wafer can be carried out of the heat treatment furnace, the first non-oxidizing atmosphere is switched to an atmosphere containing oxygen, an oxide film having a thickness of 1 to 10 nm is formed on the surface of the SiC jig in the atmosphere containing oxygen, and the atmosphere containing oxygen is then switched to a second non-oxidizing atmosphere. A silicon wafer heat treatment method can prevent carbon contamination from a jig and an environment during a heat treatment process.Type: GrantFiled: June 26, 2014Date of Patent: July 18, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara
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Patent number: 9606030Abstract: A method for detecting a crystal defect in a silicon single crystal wafer doped with nitrogen, the silicon single crystal wafer whose initial oxygen concentration is 8 ppma (JEIDA) or lower. The method further includes the steps of: making a crystal defect of defect size of 25 nm or smaller apparent and detectable by implanting oxygen into the crystal defect by performing heat treatment on the silicon single crystal wafer in an oxygen atmosphere; and detecting the crystal defect of the silicon single crystal wafer after the heat treatment temperature is set such that, when the ratio between the oxygen solid solubility and the initial oxygen concentration of the silicon single crystal wafer heat treatment is set at ?=the oxygen solid solubility/the initial oxygen concentration, ? falls within a range from 1 to 3.Type: GrantFiled: June 18, 2012Date of Patent: March 28, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi
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Publication number: 20160130718Abstract: A silicon wafer heat treatment method includes: placing a silicon wafer on a SiC jig and into a heat treatment furnace; performing heat treatment on the silicon wafer in the heat treatment furnace in a first non-oxidizing atmosphere; reducing the temperature; and carrying the silicon wafer out of the heat treatment furnace. In the heat reduction step, after the temperature is reduced to the temperature at which the silicon wafer can be carried out of the heat treatment furnace, the first non-oxidizing atmosphere is switched to an atmosphere containing oxygen, an oxide film having a thickness of 1 to 10 nm is formed on the surface of the SiC jig in the atmosphere containing oxygen, and the atmosphere containing oxygen is then switched to a second non-oxidizing atmosphere. A silicon wafer heat treatment method can prevent carbon contamination from a jig and an environment during a heat treatment process.Type: ApplicationFiled: June 26, 2014Publication date: May 12, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng QU, Fumio TAHARA
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Publication number: 20150287630Abstract: A method of manufacturing an SOI wafer, includes, before forming an oxide film, heat treating a prepared silicon wafer at a temperature ranging from 1100° C. to 1250° C. under an oxidizing atmosphere for 30 minutes to 120 minutes and polishing a surface of the silicon wafer subjected to the heat treatment, which will become a bonding interface. The method can sufficiently dissolve defects in a bond wafer in SOI-wafer manufacture and manufacture an SOI wafer with few faults such as defects. The method also can repeatedly reuse a separated wafer, which is produced as a by-product in the ion implantation separation method, as the bond wafer.Type: ApplicationFiled: September 12, 2013Publication date: October 8, 2015Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi
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Patent number: 8916953Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.Type: GrantFiled: January 6, 2012Date of Patent: December 23, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Shu Sugisawa
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Publication number: 20140355009Abstract: A measuring apparatus includes a supporting column, a securing assembly, and a pair of measuring elements. The securing assembly is movably located on the supporting column at a predetermined height. The pair of measuring elements is secured on the securing assembly opposite to each other. The measuring elements receive a workpiece and transmit lasers to the workpiece respectively.Type: ApplicationFiled: January 16, 2014Publication date: December 4, 2014Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.Inventors: KUEI-YANG LIN, MING-SHAN CAO, FAN-JIAN ZENG, BAO-FENG QU
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Patent number: 8900971Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.Type: GrantFiled: January 6, 2012Date of Patent: December 2, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
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Patent number: 8877609Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.Type: GrantFiled: April 10, 2012Date of Patent: November 4, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
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Publication number: 20140120695Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.Type: ApplicationFiled: April 10, 2012Publication date: May 1, 2014Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yuuki Ooi, Wei Feng Qu, Tsuyoshi Ohtsuki, Kyoko Mitani, Fumio Tahara
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Publication number: 20140119399Abstract: A method for detecting a crystal defect in a silicon single crystal wafer doped with nitrogen, the silicon single crystal wafer whose initial oxygen concentration is 8 ppma (JEIDA) or lower. The method further includes the steps of: making a crystal defect of defect size of 25 nm or smaller apparent and detectable by implanting oxygen into the crystal defect by performing heat treatment on the silicon single crystal wafer in an oxygen atmosphere; and detecting the crystal defect of the silicon single crystal wafer after the heat treatment temperature is set such that, when the ratio between the oxygen solid solubility and the initial oxygen concentration of the silicon single crystal wafer heat treatment is set at ?=the oxygen solid solubility/the initial oxygen concentration, ? falls within a range from 1 to 3.Type: ApplicationFiled: June 18, 2012Publication date: May 1, 2014Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi
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Publication number: 20130341763Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.Type: ApplicationFiled: January 6, 2012Publication date: December 26, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yuuki Ooi, Wei Feng Qu, Tsuyoshi Ohtsuki, Kyoko Mitani, Fumio Tahara
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Publication number: 20130264685Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.Type: ApplicationFiled: January 6, 2012Publication date: October 10, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Shu Sugisawa
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Publication number: 20070118926Abstract: The present invention provides a novel plant engineered to have a broad spectrum of resistance to plant virus infection by transforming the plant with a polynucleotide construct having an RNA dependant RNA polymerase 6 operably linked to a promoter sequence to allow expression of RNA dependant RNA polymerase 6 in the plant. Also disclosed is a method for conferring on a plant resistance to a broad spectrum of plant virus infection by transforming the plant with a polynucleotide construct having an RNA dependant RNA polymerase 6 operably linked to a promoter sequence.Type: ApplicationFiled: November 20, 2006Publication date: May 24, 2007Inventors: Thomas Morris, Feng Qu