Patents by Inventor Feng-Wei Kuo

Feng-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11756875
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiwei Song, Chan-Hong Chern, Feng-Wei Kuo, Lan-Chou Cho, Stefan Rusu
  • Patent number: 11749625
    Abstract: A semiconductor structure includes a first redistribution structure, wherein the first redistribution structure includes first conductive pattern. The semiconductor structure further includes a die over the first redistribution structure. The semiconductor structure further includes a molding over the first redistribution structure, wherein the molding surrounds the die, and the molding has a first dielectric constant. The semiconductor structure further includes a dielectric member extending through the molding, wherein the dielectric member has a second dielectric constant different from the first dielectric constant. The semiconductor structure further includes a second redistribution structure over the die, the dielectric member and the molding, wherein the second redistribution layer includes an antenna over the dielectric member, and the antenna is electrically connected to the die.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Patent number: 11740492
    Abstract: A method of forming semiconductor device includes forming an active layer in a substrate including forming components of one or more transistors; forming an MD and gate (MDG) layer over the active layer including forming a gate line; forming a metal-to-S/D (MD) contact structure; and forming a waveguide between the gate line and the MD contact structure; forming a first interconnection layer over the MDG layer including forming a first via contact structure over the gate line; forming a second via contact structure over the MD contact structure; and forming a heater between the first and second via contact structures and over the waveguide.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho
  • Publication number: 20230268301
    Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Hui-Yu Lee
  • Publication number: 20230260978
    Abstract: A package structure includes a photonic die, an electronic die and a gap filling layer. The photonic die includes a dielectric layer, a silicon layer, a reflector structure and a plurality of connection pads. The silicon layer is disposed on the dielectric layer, wherein the silicon layer includes a grating coupler having a plurality of first trench patterns with a first depth and a plurality of second trench patterns with a second depth, wherein the first depth is different than the second depth. The reflector structure is embedded in the dielectric layer below the grating coupler. The connection pads are disposed over the dielectric layer. The electronic die is disposed on the photonic die, wherein the electronic die includes a plurality of bonding pads bonded to the connection pads of the photonic die. The gap filling layer is disposed on the photonic die and surrounding the electronic die.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou
  • Patent number: 11719885
    Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao, Robert Bogdan Staszewski, Jianglin Du
  • Patent number: 11714239
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Publication number: 20230239129
    Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Huan-Neng CHEN, William Wu SHEN, Chewn-Pu JOU, Feng Wei KUO, Lan-Chou CHO, Tze-Chiang HUANG, Jack LIU, Yun-Han LEE
  • Patent number: 11703379
    Abstract: A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chewn-Pu Jou, Feng Wei Kuo, Huan-Neng Chen, Lan-Chou Cho
  • Publication number: 20230221488
    Abstract: A thermally tunable waveguide including an optical waveguide and a heater is provided. The optical waveguide includes a phase shifter. The heater is disposed over the optical waveguide. The heater includes a heating portion, pad portions and tapered portions. The heating portion overlaps with the phase shifter of the optical waveguide. The pad portions are disposed aside of the heating portion. Each of the pad portions is connected to the heating portion through one of the tapered portions respectively.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Publication number: 20230204862
    Abstract: An optical coupler is provided. The optical coupler includes: a first optical structure, and a second optical structure disposed over the first optical structure. The first optical structure includes: a first substrate, a first cladding layer disposed on the first substrate, and a first waveguide disposed on the first cladding layer. The first waveguide includes a first coupling portion, and the first coupling portion including a first taper part. The second optical structure includes: a second substrate, a dielectric layer disposed on the second substrate; and a second waveguide disposed on the dielectric layer. The second waveguide includes a second coupling portion, and the second coupling portion including a second taper part. The second taper part is disposed on and optically coupled with the first taper part, and a taper direction of the first taper part is the same as a taper direction of the second taper part.
    Type: Application
    Filed: March 3, 2023
    Publication date: June 29, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou, Cheng-Tse Tang, Hung-Yi Kuo
  • Patent number: 11688685
    Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Chih-Hang Tung, Chen-Hua Yu, Chewn-Pu Jou, Feng Wei Kuo
  • Publication number: 20230194908
    Abstract: An optical modulator includes a carrier and a waveguide disposed on the carrier. The waveguide includes a first optical coupling region, a second optical coupling region, first regions, and second regions. The first optical coupling region is doped with first dopants. The second optical coupling region abuts the first optical coupling region and is doped with second dopants. The first dopants and the second dopants are of different conductivity type. The first regions are doped with the first dopants and are arrange adjacent to the first optical coupling region. The first regions have respective increasing doping concentrations as distances of the first regions increase from the first optical coupling region. The second regions are doped with the second dopants and are arranged adjacent to the second optical coupling region. The second regions have respective increasing doping concentrations as distances of the second regions increase from the second optical coupling region.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 22, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng-Wei KUO, Huan-Neng Chen, Min-Hsiang Hsu
  • Patent number: 11675957
    Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
  • Patent number: 11670610
    Abstract: A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Hui-Yu Lee
  • Patent number: 11641064
    Abstract: The present disclosure relates to a semiconductor package device including a stacked antenna structure with a high-k laminated dielectric layer separating antenna and ground planes, and a method of manufacturing the structure. A semiconductor die is laterally encapsulated within an insulating structure comprising a first redistributions structure. A second redistribution structure is disposed over and electrically coupled to the first redistribution structure and the die. The second redistribution structure includes the stacked antenna structure which includes first and second conductive planes separated by a high dielectric constant laminated dielectric structure. The first conductive plane includes openings and the second conductive plane is configured to transmit and receive electromagnetic waves through the openings in the first conductive plane.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: May 2, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shiang Liao, Feng Wei Kuo
  • Patent number: 11640033
    Abstract: An optical coupler is provided. The optical coupler includes: a first optical structure, and a second optical structure disposed over the first optical structure. The first optical structure includes: a first substrate, a first cladding layer disposed on the first substrate, and a first waveguide disposed on the first cladding layer. The first waveguide includes a first coupling portion, and the first coupling portion including a first taper part. The second optical structure includes: a second substrate, a dielectric layer disposed on the second substrate; and a second waveguide disposed on the dielectric layer. The second waveguide includes a second coupling portion, and the second coupling portion including a second taper part. The second taper part is disposed on and optically coupled with the first taper part, and a taper direction of the first taper part is the same as a taper direction of the second taper part.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 2, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou, Cheng-Tse Tang, Hung-Yi Kuo
  • Patent number: 11635651
    Abstract: The invention provides a display panel, which includes a first substrate, a second substrate, a liquid crystal layer, a light shielding pattern layer and a plurality of pixel structures. The liquid crystal layer is disposed between the first substrate and the second substrate, and includes a plurality of negative liquid crystal molecules. Each of the pixel structures includes a first electrode and a second electrode. The first electrode has an electrode opening and a first finger portion extending into the electrode opening. The second electrode has two second finger portions overlapping the electrode opening. The first finger portion and the two second finger portions are alternately arranged along a first direction inside the electrode opening and extend in a second direction.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 25, 2023
    Assignee: HannStar Display Corporation
    Inventors: Chia-Hua Yu, Kun Tsai Huang, Feng-Wei Kuo, Luo-Yi Wu
  • Patent number: 11637078
    Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Wen-Shiang Liao, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, William Wu Shen
  • Patent number: 11635643
    Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Feng-Wei KUo, Min-Hsiang Hsu, Lan-Chou Cho, Chewn-Pu Jou, Wen-Shiang Liao