Patents by Inventor Fernando Santos
Fernando Santos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984429Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.Type: GrantFiled: September 30, 2021Date of Patent: May 14, 2024Assignee: NXP USA, Inc.Inventors: Yun Wei, Scott Duncan Marshall, Lakshminarayan Viswanathan, Taek Kyu Kim, Ricardo Uscola, Fernando A. Santos
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Patent number: 11942300Abstract: A fuse shield features a cylindrical body, a first cap cover, a second cap cover, and a stop region. The cylindrical body is adapted to be placed over and partially surround a cylindrical fuse. The cylindrical body is sandwiched between the first and second cap covers. The stop region is located on an edge of the first cap cover to limit rotation of the cylindrical fuse to a first degree in one direction on a flat surface.Type: GrantFiled: January 19, 2023Date of Patent: March 26, 2024Assignee: Littelfuse, Inc.Inventors: Sheila Marie Vinas Bayer, Randy Capablanca Servancia, Fernando Isip Arce, Jr., Edwin Canido Aberin, Roel Santos Retardo, Francisco Rivera De Guia, Jr.
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Publication number: 20240097522Abstract: The present invention relates to an axial flux electric machine (1) with a stator wound with a plurality of wound cores (8) arranged on a support disk (10), in which the support disk (10) and the plurality of wound cores (8) are encapsulated in a resin (9), in which at least one continuous coiled cooling channel (12) is formed in the resin (9), during or after the encapsulation process, on each side of the support disk (10). Each continuous coiled cooling channel (12) passes close to at least one of the surfaces of each portion of the wound core (9) without touching said at least one surface.Type: ApplicationFiled: January 31, 2022Publication date: March 21, 2024Inventors: Edson Carlos PERES DE OLIVEIRA, Fernando Andre Lindroth DAUNER, Rodrigo Souza AGUIAR, Samuel Santos BORGES, Valmir Luís STOINSKI
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Patent number: 11932719Abstract: A biodegradable based polymers for the production of biodegradable medical applications is provided. The biobased material has a copolymer constituted by dextran modified with glycidyl methacrylate and poly (#-caprolactone) modified with 2-isocyanatoethylmethacrylate, which are combined in different formulations and used to produce membranes, 3-D scaffolds and hollow tubes that can be used as biomedical devices for diverse applications, such as drug delivery systems, tissue engineering scaffolds, repair and regeneration of peripheral nerves, among others.Type: GrantFiled: June 6, 2019Date of Patent: March 19, 2024Assignees: UNIVERSIDADE DE COMIBRA, UNIVERSIDADE DO PORTOInventors: Jorge Fernando Jordao Coelho, Ana Clotilde Amaral Loureiro Da Fonseca, Armenio Coimbra Serra, Ana Catarina Da Silva Pinho, Jose Domingos Santos, Ana Colette Pereira De Castro Osorio Mauricio, Ana Rita Caseiro Santos, Silvia Marlene Almeida Santos Pedrosa, Mariana Esteves Vieira Branquinho, Rui Damasio Alvites, Irina Ferraz Amorim Cruz
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Publication number: 20230197645Abstract: Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Zhiwei Gong, LI Li, Lu Li, Lakshminarayan Viswanathan, Fernando A. Santos, Burton Jesse Carpenter
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Publication number: 20230115340Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.Type: ApplicationFiled: September 30, 2021Publication date: April 13, 2023Inventors: Yun Wei, Scott Duncan Marshall, Lakshminarayan Viswanathan, Taek Kyu Kim, Ricardo Uscola, Fernando A. Santos
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Patent number: 11621231Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.Type: GrantFiled: April 15, 2022Date of Patent: April 4, 2023Assignee: NXP USA, Inc.Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
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Patent number: 11581241Abstract: A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.Type: GrantFiled: December 29, 2020Date of Patent: February 14, 2023Assignee: NXP USA, Inc.Inventors: Boon Yew Low, Fernando A. Santos, Li Li, Fui Yee Lim, Lan Chu Tan
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Patent number: 11437276Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.Type: GrantFiled: July 3, 2020Date of Patent: September 6, 2022Assignee: NXP USA, Inc.Inventors: Jaynal A Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
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Publication number: 20220238450Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
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Publication number: 20220208646Abstract: A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Boon Yew Low, Fernando A. Santos, Li Li, Fui Yee Lim, Lan Chu Tan
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Patent number: 11342275Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.Type: GrantFiled: October 22, 2020Date of Patent: May 24, 2022Assignee: NXP USA, Inc.Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
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Patent number: 11343919Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.Type: GrantFiled: July 22, 2019Date of Patent: May 24, 2022Assignee: NXP USA, Inc.Inventors: Fernando A. Santos, Audel Sanchez, Lakshminarayan Viswanathan, Jerry Lynn White
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Publication number: 20220130768Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.Type: ApplicationFiled: October 22, 2020Publication date: April 28, 2022Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
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Publication number: 20200335398Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.Type: ApplicationFiled: July 3, 2020Publication date: October 22, 2020Inventors: Jaynal A. Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
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Patent number: 10795531Abstract: A method, an apparatus, a system, and a computer program product for synchronizing a display context across a plurality of customer service applications. A computer system receives a service request from a first customer over one of a plurality of communication channels. The computer system accesses a first customer service ticket within a first customer context displayed in a first graphical user interface of a first customer service application. The computer system accesses a set of customer service tools within the first customer context displayed in a second graphical user interface of a second application. The computer system synchronizes the display context across both the first graphical user interface of the first application and the second graphical user interface of the second application.Type: GrantFiled: February 1, 2019Date of Patent: October 6, 2020Assignee: ADP, LLCInventors: Shawn Murphy, Michael Syrquin, Fernando Santos, Jennifer Herman, Diego Bonilla, Dianne Frommelt, Sarah Iodice, Allison Harrison, Charles Lafferty, Kimberly Wyman, Nancy Ressler, Steven Petros
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Patent number: 10741446Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.Type: GrantFiled: July 5, 2017Date of Patent: August 11, 2020Assignee: NXP USA, Inc.Inventors: Jaynal A Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
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Publication number: 20200249797Abstract: A method, an apparatus, a system, and a computer program product for synchronizing a display context across a plurality of customer service applications. A computer system receives a service request from a first customer over one of a plurality of communication channels. The computer system accesses a first customer service ticket within a first customer context displayed in a first graphical user interface of a first customer service application. The computer system accesses a set of customer service tools within the first customer context displayed in a second graphical user interface of a second application. The computer system synchronizes the display context across both the first graphical user interface of the first application and the second graphical user interface of the second application.Type: ApplicationFiled: February 1, 2019Publication date: August 6, 2020Inventors: Shawn Murphy, Michael Syrquin, Fernando Santos, Jennifer Herman, Diego Bonilla, Dianne Frommelt, Sarah Iodice, Allison Harrison, Charles Lafferty, Kimberly Wyman, Nancy Ressler, Steven Petros
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Publication number: 20200236539Abstract: A method for protecting user privacy on a mobile communication device, such as a smart phone or tablet computing device, is provided. The method includes performing a facial recognition of a user in order to authenticate the user for a normal operation of the device; displaying, on a screen of the device, first content that corresponds to the normal operation of the device by the authenticated user; detecting a presence of a face of a second person that is different from the authenticated user; and displaying, on the screen, second content that corresponds to a predetermined safety screen, such that the first content is hidden from being displayed. The method may be implemented such that the safety screen is displayed in response to detecting an aversion of the eyes of the authenticated user.Type: ApplicationFiled: January 17, 2020Publication date: July 23, 2020Applicant: JPMorgan Chase Bank, N.A.Inventors: Fernando SANTOS, Jarryd Gregory Felix AUBERT, Scott ANDREW RUNCIMAN, Sheryl GALLACHER
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Patent number: D897620Type: GrantFiled: February 19, 2019Date of Patent: September 29, 2020Assignee: The Libman CompanyInventors: Andrew Libman, Carlos Aguiar, Fernando Santos, Aaron Libman, Jon Franklin