Patents by Inventor Flavio Francesco Villa
Flavio Francesco Villa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12134556Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.Type: GrantFiled: November 23, 2021Date of Patent: November 5, 2024Assignees: STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.Inventors: Enri Duqi, Lorenzo Baldo, Paolo Ferrari, Benedetto Vigna, Flavio Francesco Villa, Laura Maria Castoldi, Ilaria Gelmi
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Patent number: 12058938Abstract: A process for manufacturing a MEMS piezoelectric device includes: forming a membrane at a first surface of wafer of semiconductor material further having a second surface (the first and second surfaces being opposite along a vertical axis and extending parallel to a horizontal plane formed by first and second horizontal axes); forming a cavity within the wafer so that the membrane is suspended above the cavity; forming a piezoelectric material layer above a first surface of the membrane; forming an electrode arrangement in contact with the piezoelectric material layer; and forming a proof mass coupled to a second surface of the membrane opposite to the first surface along the vertical axis. The proof mass deforms the membrane in response to environmental mechanical vibrations. Forming the proof mass includes forming a connection element at a central position between the membrane and the proof mass in the direction of the vertical axis.Type: GrantFiled: April 18, 2022Date of Patent: August 6, 2024Assignee: STMicroelectronics S.r.l.Inventors: Maria Fortuna Bevilacqua, Flavio Francesco Villa, Rossana Scaldaferri, Valeria Casuscelli, Andrea Di Matteo, Dino Faralli
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Publication number: 20240124299Abstract: Process for manufacturing a MEMS device, including: forming a dielectric region which coats part of a semiconductive substrate of a first semiconductive wafer; forming a region which is permeable to gases and coats the dielectric region; coupling the first semiconductive wafer to a second semiconductive wafer so as to form a first chamber, which houses a first movable mass and has a pressure equal to a first value, and a second chamber, which houses a second movable mass and has a pressure equal to the first value, the permeable region facing the second chamber; selectively removing a portion of the semiconductor substrate and an underlying portion of the dielectric region, so as to expose a part of the permeable region, so as to allow gas exchanges through the permeable region; placing the first and the second semiconductive wafers in an environment with a pressure equal to a second value, so that the pressure in the second chamber becomes equal to the second value; and subsequently forming, on the exposed pType: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA
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Patent number: 11871668Abstract: A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.Type: GrantFiled: January 26, 2021Date of Patent: January 9, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Paolo Ferrari, Flavio Francesco Villa, Luca Zanotti, Andrea Nomellini, Luca Seghizzi
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Publication number: 20230389426Abstract: MEMS thermoelectric generator comprising: a thermoelectric cell including one or more thermoelectric elements partially extending on a cavity of the thermoelectric cell; a thermoplastic layer extending on the thermoelectric cell and having a top surface and a bottom surface opposite to each other along a first axis, the bottom surface facing the thermoelectric cell and the thermoplastic layer being of thermally insulating material and configured to be processed through laser direct structuring, LDS, technique; a heat sink configured to exchange heat with the thermoelectric cell interposed, along the first axis, between the heat sink and the thermoplastic layer; and a thermal via of metal material, extending through the thermoplastic layer from the top surface to the bottom surface so that it is superimposed, along the first axis, on the cavity, wherein the thermoelectric cell may exchange heat with a thermal source through the thermal via.Type: ApplicationFiled: May 16, 2023Publication date: November 30, 2023Applicant: STMicroelectronics S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Marco DEL SARTO
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Publication number: 20230301191Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectriType: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Lucia ZULLINO, Andrea NOMELLINI, Luca SEGHIZZI, Luca ZANOTTI, Bruno MURARI, Martina SCOLARI
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Patent number: 11696504Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectriType: GrantFiled: May 14, 2021Date of Patent: July 4, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Paolo Ferrari, Flavio Francesco Villa, Lucia Zullino, Andrea Nomellini, Luca Seghizzi, Luca Zanotti, Bruno Murari, Martina Scolari
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Publication number: 20230061430Abstract: Method for manufacturing a micro-electro-mechanical system, MEMS, integrating a first MEMS device and a second MEMS device. The first MEMS device is a capacitive pressure sensor and the second MEMS device is an inertial sensor. The steps of manufacturing the first and second MEMS devices are, at least partly, shared with each other, resulting in a high degree of integration on a single die, and allowing to implement a manufacturing process with high yield and controlled costs.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Lorenzo CORSO, Flavio Francesco VILLA, Silvia NICOLI, Luca LAMAGNA
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Publication number: 20230064114Abstract: The present disclosure is directed to a method for manufacturing a micro-electro-mechanical device. The method includes the steps of forming, on a substrate, a first protection layer of crystallized aluminum oxide, impermeable to HF; forming, on the first protection layer, a sacrificial layer of silicon oxide removable with HF; forming, on the sacrificial layer, a second protection layer of crystallized aluminum oxide; exposing a sacrificial portion of the sacrificial layer; forming, on the sacrificial portion, a first membrane layer of a porous material, permeable to HF; forming a cavity by removing the sacrificial portion through the first membrane layer; and sealing pores of the first membrane layer by forming a second membrane layer on the first membrane layer.Type: ApplicationFiled: August 23, 2022Publication date: March 2, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Roberto CAMPEDELLI, Luca LAMAGNA, Enri DUQI, Mikel AZPEITIA URQUIA, Silvia NICOLI, Maria Carolina TURI
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Publication number: 20220411256Abstract: MEMS device formed in a semiconductor body which is monolithic and has a first and a second main surface. A buried cavity extends into the semiconductor body below and at a distance from the first main surface. A diaphragm extends between the buried cavity and the first main surface of the semiconductor body and has a buried face facing the buried cavity. A diaphragm insulating layer extends on the buried face of the diaphragm and a lateral insulating region extends into the semiconductor body along a closed line, between the first main surface and the diaphragm insulating layer, above the buried cavity. The lateral insulating region laterally delimits the diaphragm and forms, with the diaphragm insulating layer, a diaphragm insulating region which delimits the diaphragm and electrically insulates it from the rest of the wafer.Type: ApplicationFiled: June 17, 2022Publication date: December 29, 2022Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Enri DUQI, Igor VARISCO, Filippo D'ERCOLI
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Patent number: 11417827Abstract: A MEMS piezoelectric device includes a monolithic semiconductor body having first and second main surfaces extending parallel to a horizontal plane formed by first and second horizontal axes. A housing cavity is arranged within the monolithic semiconductor body. A membrane is suspended above the housing cavity at the first main surface. A piezoelectric material layer is arranged above a first surface of the membrane with a proof mass coupled to a second surface, opposite to the first surface, along the vertical axis. An electrode arrangement is provided in contact with the piezoelectric material layer. The proof mass causes deformation of the piezoelectric material layer in response to environmental mechanical vibrations. The proof mass is coupled to the membrane by a connection element arranged, in a central position, between the membrane and the proof mass in the direction of the vertical axis.Type: GrantFiled: December 11, 2018Date of Patent: August 16, 2022Assignee: STMicroelectronics S.r.l.Inventors: Maria Fortuna Bevilacqua, Flavio Francesco Villa, Rossana Scaldaferri, Valeria Casuscelli, Andrea Di Matteo, Dino Faralli
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Publication number: 20220246832Abstract: A MEMS piezoelectric device includes a monolithic semiconductor body having first and second main surfaces extending parallel to a horizontal plane formed by first and second horizontal axes. A housing cavity is arranged within the monolithic semiconductor body. A membrane is suspended above the housing cavity at the first main surface. A piezoelectric material layer is arranged above a first surface of the membrane with a proof mass coupled to a second surface, opposite to the first surface, along the vertical axis. An electrode arrangement is provided in contact with the piezoelectric material layer. The proof mass causes deformation of the piezoelectric material layer in response to environmental mechanical vibrations. The proof mass is coupled to the membrane by a connection element arranged, in a central position, between the membrane and the proof mass in the direction of the vertical axis.Type: ApplicationFiled: April 18, 2022Publication date: August 4, 2022Applicant: STMicroelectronics S.r.l.Inventors: Maria Fortuna BEVILACQUA, Flavio Francesco VILLA, Rossana SCALDAFERRI, Valeria CASUSCELLI, Andrea DI MATTEO, Dino FARALLI
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Publication number: 20220169498Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.Type: ApplicationFiled: November 23, 2021Publication date: June 2, 2022Applicants: STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.Inventors: Enri DUQI, Lorenzo BALDO, Paolo FERRARI, Benedetto Vigna, Flavio Francesco VILLA, Laura Maria CASTOLDI, Ilaria GELMI
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Patent number: 11294168Abstract: A MEMS micromirror device includes a monolithic body of semiconductor material having a first main surface and a second main surface, with the monolithic body having an opening extending from the second main surface and including a suspended membrane of monocrystalline semiconductor material extending between the opening and the first main surface of the monolithic body. The suspended membrane includes a supporting frame and a mobile mass carried by the supporting frame and rotatable about an axis parallel to the first main surface, with the mobile mass having a width less than a width of the opening. A reflecting region extends over the mobile mass.Type: GrantFiled: August 5, 2020Date of Patent: April 5, 2022Assignee: STMicroelectronics S.r.l.Inventors: Enri Duqi, Lorenzo Baldo, Roberto Carminati, Flavio Francesco Villa
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Patent number: 11251580Abstract: An integrated optical device, including: a semiconductor body delimited by a top surface; and at least one buried cavity, which extends in the semiconductor body, at a distance from the top surface, so as to delimit at the bottom a front semiconductor region, which functions as an optical guide.Type: GrantFiled: October 30, 2019Date of Patent: February 15, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Flavio Francesco Villa, Guido Chiaretti, Gabriele Barlocchi
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Publication number: 20210359189Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectriType: ApplicationFiled: May 14, 2021Publication date: November 18, 2021Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Lucia ZULLINO, Andrea NOMELLINI, Luca SEGHIZZI, Luca ZANOTTI, Bruno MURARI, Martina SCOLARI
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Publication number: 20210242387Abstract: A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.Type: ApplicationFiled: January 26, 2021Publication date: August 5, 2021Applicant: STMICROELECTRONICS S.R.L.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Luca ZANOTTI, Andrea NOMELLINI, Luca SEGHIZZI
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Publication number: 20210143286Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Applicant: STMicroelectronics S.r.l.Inventors: Flavio Francesco VILLA, Marco MORELLI, Marco MARCHESI, Simone Dario MARIANI, Fabrizio Fausto Renzo TOIA
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Patent number: 10961117Abstract: A process for manufacturing a microelectromechanical device envisages: providing a wafer of semiconductor material; forming a buried cavity, completely contained within the wafer, and a structural layer formed by a surface portion of the wafer and suspended over the buried cavity; forming first trenches through the structural layer as far as the buried cavity, which define the suspended structure in the structural layer; filling the first trenches and the buried cavity with sacrificial material; forming a closing structure above the structural layer; removing the sacrificial material from the first trenches and from the buried cavity to release the suspended structure, the suspended structure being isolated and buried within the wafer in a buried environment formed by the first trenches and by the buried cavity.Type: GrantFiled: June 4, 2019Date of Patent: March 30, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Enri Duqi, Lorenzo Baldo, Flavio Francesco Villa, Gabriele Barlocchi
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Patent number: 10930799Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.Type: GrantFiled: January 14, 2019Date of Patent: February 23, 2021Assignee: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Marco Morelli, Marco Marchesi, Simone Dario Mariani, Fabrizio Fausto Renzo Toia