Process for manufacturing an SOI wafer by annealing and oxidation of buried channels
A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
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This application claims priority from European patent application No. 01830820.5, filed Dec. 28, 2001, which is incorporated herein by reference.
TECHNICAL FIELDThe present invention relates generally to semiconductor processing, and more particularly to a process for manufacturing an SOI wafer annealing and oxidation of buried channels.
BACKGROUNDAs is known, according to a solution that is currently very widespread in the sector of the microelectronics industry, the substrate of integrated devices is obtained from monocrystalline silicon wafers. In recent years, as an alternative to wafers made of silicon alone, composite wafers have been proposed, namely the so called silicon-on-insulator (SOI) wafers, consisting of two silicon layers, one of which is thinner than the other, separated by a silicon dioxide layer.
However, manufacturing of SOI wafers entails some problems, especially as regards the complexity and cost of the process and the quality of the thinner silicon layer. In fact, this layer is designed to house both high-power and low-power electronic devices, and the presence of crystallographic defects may irreparably impair the efficiency of the devices.
One method for manufacturing SOI wafers that partially tackles the above problems is described in EP-A1 073 112, filed on Jul. 26, 1999 in the name of the present applicant and incorporated by reference.
This method envisages initially forming, in a substrate of semiconductor material, for example monocrystalline silicon, a plurality of trenches which are substantially parallel and are separated from one another by silicon partition walls. In order to open the trenches, the substrate is anisotropically etched using a hard mask, which comprises, for example, a pad oxide layer and a silicon nitride layer.
Subsequently, by isotropically etching silicon, the trenches are widened so as to thin out the partition walls and form cavities which extend beneath the surface of the substrate, which, at this stage, is still protected by the hard mask.
The cavities are then lined with an inhibiting silicon dioxide layer, and the hard mask is removed, thus leaving the surface of the substrate uncovered.
Next, an epitaxial growth is carried out. In this step, the silicon grows on top of the substrate and expands laterally so as to form a uniform epitaxial layer that covers the entrance of the cavities. However, the inhibiting layer prevents silicon from growing inside the cavities, which thus are not filled and form buried channels.
Using a second anisotropic etch, connection trenches are opened, which have a depth such as to reach the cavities. Through the connection trenches, a thermal oxidation step is then performed, so that the partition walls separating the cavities are completely oxidized and the cavities are filled with silicon dioxide. Thereby, a continuous insulating region is formed, which separates the substrate and the epitaxial layer.
The process taught in the above mentioned patent application yields high quality SOI wafers, above all as regards crystallographic properties of the epitaxial layer, but has some limitations.
In fact, the processing steps required for forming the insulating region are numerous and complex and render the manufacturing of the wafers costly. First, during isotropic etching for widening the trenches and forming the cavities, the surface of the substrate must be protected, in particular with the hard mask. The formation of this mask, however, requires at least one oxidation step, one silicon nitride layer deposition step, and one definition step using a further resist mask. The hard mask must moreover be removed through further special steps.
Second, before carrying out the epitaxial growth, the cavities must be lined with the inhibiting layer; otherwise, in fact, the partition walls would get thicker and subsequently could no longer be oxidized completely. In addition, it is necessary to calibrate with precision the width of the inhibiting layer, which is partially removed during removal of the hard mask.
SUMMARYTherefore, an embodiment of the present invention is a process that overcomes the drawbacks of the manufacturing process described above.
BRIEF DESCRIPTION OF THE DRAWINGSFor a better understanding of the present invention, a preferred embodiment thereof is now described, purely as a non-limiting example, with reference to the attached drawings, wherein:
The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention as defined by the appended claims. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
In
Next, the substrate 2 is etched anisotropically, for example through an STS etch, and deep trenches 5 are opened at the regions left uncovered by the mask 4, as shown in
Next, mask 4 is removed, and an epitaxial growth is performed (
As shown in
After annealing, a second masked trench etching is performed to open in the wafer 1 at least one connection trench 10 having a depth such as to reach all the buried channels 8 and a width greater than the final width S″ of the partition walls 7 (for example, 1 μm). Preferably, the connection trench 10 extends along a closed line and delimits an insulated monocrystalline silicon region 11, intended to subsequently form an active area for accommodating integrated components (
Next, thermal oxidation of the partition walls 7 and of the walls of the connection trench 10 is carried out so as to form a silicon dioxide insulating region 12. The oxygen required is fed to the buried channels 8 through the connection trench 10. In this step, the oxide regions gradually grow at the expense of the silicon regions that form the partition walls 7 and the walls of the connection trench 10. In particular, the partition walls 7 are completely oxidized, by virtue of the width reduction caused by the previous annealing step. As shown in
Next (
The wafer 1 of
According to a different embodiment of the invention, shown in
Next, epitaxial growth and annealing are carried out, as above described. In particular, during the epitaxial growth, the deep trenches 18 are closed, and a deep cavity 19 is formed, while during annealing, the columns 17 are thinned out in a central portion, thus assuming an hourglass shape (
The process is then completed as previously described. In particular, a connection trench 20 is opened, the columns 17 are completely oxidized so as to form an insulating region 21 which delimits an insulated silicon region 22, and the buried cavity 19 is filled with TEOS oxide, thus forming filling regions 23.
The process described herein is extremely simple, at the same time it enables manufacturing of SOI wafers that are free from crystallographic defects. In fact, the required processing steps are not so numerous as in known processes and can be easily included in standard processes for manufacturing integrated devices.
Particularly advantageous is the use of the annealing step, which, according to the described embodiments of the invention, is performed instead of isotropic etching previously used for widening the trenches. The formation of structures, such as walls or columns, delimited by cavities and embedded in the silicon is in itself simple, in so far as it requires only one masked trench etch and one epitaxial growth. The subsequent annealing step allows the surfaces of the buried cavities (buried channels 8 and buried cavity 19) to be modified, widening the latter and reducing the width of the silicon structures (partition walls 7 and columns 17), so that the silicon structures can then be oxidized. The surface of the wafer is not, however, involved and thus does not have to be protected; consequently, all the steps for forming and removing hard masks are eliminated. Also the need for the inhibiting layer is overcome: since the annealing follows epitaxial growth, forming silicon inside the deep trenches 5 (or the communicating trenches 18) is within bearable limits, provided that these deep trenches are not filled completely.
In addition, the atmosphere entrapped inside the buried cavities is the same as used for the epitaxial growth, namely an atmosphere with a high hydrogen concentration. In practice, the annealing step, which normally requires the use of a hydrogen oven, can be performed using a standard thermal process. Furthermore, with a single thermal process it is possible to carry out both annealing and other manufacturing steps that are normally envisaged for manufacturing components and/or integrated circuits; for example, annealing could be carried out simultaneously with the diffusion of a previously implanted doping species.
Finally, it is clear that numerous modifications and variations may be made to the process described and illustrated herein, all falling within the scope of the invention, as defined in the attached claims.
In particular, the process can be used for selectively insulating portions of the wafer. Alternatively, the insulating region may extend throughout the wafer.
Annealing could be carried out even before epitaxial growth. In this case, however, it would be necessary to use a hydrogen oven.
Furthermore, the initial shape of the trenches may be different from the shapes shown herein.
Claims
1. A process for manufacturing an SOI wafer, comprising the steps of:
- forming, in a wafer of semiconductor material, cavities which delimit structures of said semiconductor material; and
- oxidizing completely said structures;
- characterized by performing, before said step of oxidizing, a step of thinning out said structures through a thermal process.
2. The process according to claim 1, characterized in that said step of thinning out comprises modifying the surface distribution of said semiconductor material around said cavities.
3. The process according to claim 2, characterized in that said step of modifying comprises annealing said wafer in a deoxidizing atmosphere.
4. The process according to claim 1, characterized in that said thermal process has a controlled duration.
5. The process according to claim 1, characterized in that said step of forming cavities comprises embedding said cavities within said wafer.
6. The process according to claim 5, characterized in that said step of embedding comprises entrapping hydrogen inside said cavities.
7. The process according to claim 1, characterized in that said step of forming cavities comprises the steps of:
- opening first trenches in a substrate of said wafer; and
- performing an epitaxial growth, so as to upwardly close said first trenches with said semiconductor material.
8. The process according to claim 7, characterized in that said structures comprise walls arranged side-by-side and separated from each other by said first trenches.
9. The process according to claim 8, characterized in that said first trenches are substantially rectilinear and have a height and a width smaller than said height, and in that the ratio between said height and said width is not smaller than 5.
10. The process according to claim 8, characterized in that said width is substantially equal to a width of said walls.
11. The process according to claim 8, characterized in that, at the end of said step of thinning out, said cavities have a substantially circular cross-section.
12. The process according to claim 7, characterized in that said structures comprise columns.
13. The process according to claim 1, characterized in that, before said step of oxidizing, at least one second trench having a depth reaching said cavities is opened.
14. The process according to claim 12, characterized in that said second trench extends along a closed line and delimits an insulated region.
15. The process according to claim 1, characterized in forming, inside said cavities, a filling region of a dielectric material.
16. The process according to claim 15, characterized in that said dielectric material is TEOS oxide.
17. A method, comprising:
- forming in a semiconductor material cavities separated by walls;
- thermally annealing the semiconductor material after forming the cavities; and
- converting the walls into insulators after thermally annealing the semiconductor material.
18. The method of claim 17 wherein forming the cavities comprises:
- forming trenches in a first region of the semiconductor material; and
- forming a second region of the semiconductor material over the first region after forming the trenches.
19. The method of claim 17 wherein forming the cavities comprises forming the cavities such that they hold a deoxidizing atmosphere.
20. The method of claim 17 wherein:
- each of the cavities has a cross-sectional shape; and
- thermally annealing the semiconductor material changes the cross-sectional shape of at least one of the cavities.
21. The method of claim 17, further comprising filling the cavities with an insulator after converting the walls to insulators.
22. The method of claim 17 wherein converting the walls into insulators comprises:
- forming a cavity opening around a surface region of the semiconductor material; and
- oxidizing the walls via the cavity opening.
23. The method of claim 17, further comprising:
- wherein converting the walls into insulators comprises, forming a cavity opening around a surface region of the semiconductor material, and oxidizing the walls via the cavity opening; and filling the cavities with an insulator after oxidizing the walls.
24. The method of claim 17 wherein thermally annealing the semiconductor material comprises heating the semiconductor materially at substantially 1150° C. for substantially five hours.
25. A semiconductor structure, comprising:
- a first semiconductor region;
- a second semiconductor region disposed on the first semiconductor region; and
- a dielectric region disposed between the first and second semiconductor regions and including, a first insulator material, at least one cavity disposed within the first insulator material, and a second insulator material that is different than the first insulator material and that is disposed within the at least one cavity.
26. The semiconductor structure of claim 25 wherein the first and second semiconductor regions comprise silicon.
27. The semiconductor structure of claim 25, further comprising a semiconductor device disposed in the second semiconductor region.
28. The semiconductor structure of claim 25 wherein:
- the first semiconductor region comprises an inner periphery;
- the second semiconductor region comprises an outer periphery and is disposed within the inner perhiphery of the first semiconductor region; and
- a portion of the dielectric region is disposed between the inner periphery of the first semiconductor region and the outer periphery of the second semiconductor region.
29. The semiconductor structure of claim 25 wherein:
- the first semiconductor region comprises an inner periphery;
- the second semiconductor region comprises an outer periphery and is disposed within the inner perhiphery of the first semiconductor region; and
- a portion of the dielectric region is disposed between the inner periphery of the first semiconductor region and the outer periphery of the second semiconductor region, the portion including an inner region that intersects the at least one cavity and that is filled with the second insulator material and including an outer region that is filled with the first insulator material.
30. The semiconductor structure of claim 25 wherein the dielectric region further comprises a trench that extends between a surface of the dielectric region and the at least one cavity and that is filled with the second insulator material.
31. The semiconductor structure of claim 25 wherein:
- the first insulator material comprises silicon dioxide; and
- the second insulator material comprises tetraethylorthosilicate (TEOS).
32. The semiconductor structure of claim 25 wherein the at least one cavity has a substantially circular cross section.
Type: Application
Filed: Dec 20, 2002
Publication Date: Jan 26, 2006
Patent Grant number: 7294536
Applicant:
Inventors: Flavio Villa (Milano), Gabriele Barlocchi (Cornaredo), Pietro Corona (Roma)
Application Number: 10/327,702
International Classification: H01L 29/00 (20060101);