Patents by Inventor Fong Lim

Fong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210286562
    Abstract: A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 16, 2021
    Inventors: Ping-Kun WANG, Shao-Ching LIAO, Chien-Min WU, Chia Hua HO, Frederick CHEN, He-Hsuan CHAO, Seow-Fong LIM
  • Patent number: 11088711
    Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 10, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
  • Publication number: 20210233839
    Abstract: An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Paul Armand Asentista Calo, Tek Keong Gan, Ser Yee Keh, Tien Heng Lem, Fong Lim, Michael Stadler, Mei Qi Tay
  • Patent number: 11069386
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 20, 2021
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 11055021
    Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 6, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, Chien-Min Wu, Chia Hua Ho, Frederick Chen, He-Hsuan Chao, Seow-Fong Lim
  • Patent number: 11010245
    Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Seow-Fong Lim, Ngatik Cheung, Chi-Shun Lin
  • Publication number: 20210141689
    Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
  • Patent number: 10937495
    Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
  • Publication number: 20210013906
    Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 14, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
  • Publication number: 20210005255
    Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 7, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
  • Patent number: 10853167
    Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 1, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
  • Publication number: 20200335144
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Application
    Filed: May 8, 2020
    Publication date: October 22, 2020
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 10811092
    Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Chuen-Der Lien, Douk-Hyoun Ryu, Ming-Huei Shieh, Seow Fong Lim
  • Publication number: 20200302973
    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
    Type: Application
    Filed: April 9, 2020
    Publication date: September 24, 2020
    Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
  • Publication number: 20200241957
    Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
  • Patent number: 10714157
    Abstract: A non-volatile memory and a reset method thereof are provided. The reset method includes: performing a first reset operation on a plurality of memory cells; recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells; performing a second reset operation on the first failure memory cells, and verifying second failure memory cells to obtain a plurality of second verifying currents; setting a first voltage modify flag according to a plurality of first ratios between the first verifying currents and the respectively corresponding second verifying currents; and adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 14, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Ngatik Cheung, Chia-Wen Cheng
  • Patent number: 10700878
    Abstract: A PUF code generation apparatus that includes a reference generator, a PUF information generation and storage array, a sensing amplifier and a writing driver is introduced. The PUF information generation and storage array includes a plurality of first memory cells each including a PUF information providing element and a PUF information storage element. The sensing amplifier compares a plurality of first electrical values read from the PUF information providing elements to a reference generated from the reference generator to generate a plurality of PUF information. The writing driver performs a write-back operation on the PUF information storage elements according to the plurality of PUF information. The sensing amplifier reads a plurality of second electrical values of the PUF information storage elements to generate a sensing result and output a PUF code according to the sensing result.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 30, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Douk-Hyoun Ryu, Seow Fong Lim
  • Patent number: 10650870
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 12, 2020
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Publication number: 20200132181
    Abstract: An electromagnetic continuously variable transmission system is provided, including: a pulley, including a first disc having an axial sleeve and a second disc, the first disc having a plurality of grooves which extend radially at one side, pulley balls being slidably received within respective ones of the grooves, the first disc having a first slope at another side, the second disc being located by the side of the first disc with the grooves; a driving shaft, disposed in the axial sleeve and the second disc, the first disc being axially slidable relative to the driving shaft; an electromagnetic assembly, disposed on the pulley, including electromagnets spacingly arranged in a part of the grooves; when each of the electromagnets is electrified and generate magnetism, each of the electromagnets magnetically attracts one of the pulley balls toward the axial sleeve.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Cho-Yu Lee, Jui-Hung Chang, Chin-Fong Lim
  • Patent number: 10622028
    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 14, 2020
    Assignee: Unity Semiconductor Corporation
    Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala