Abstract: The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: A memory device includes a plurality of memory layers and a selecting circuit configured to select a delta value corresponding to a parameter of at least one of the plurality of memory layers having fabricated thereon at least one memory cell accessed during an operation. The memory device further includes an adjusting circuit configured to adjust an access signal based at least in part on the delta value, the access signal being configured to access the at least one memory cell during the operation.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.

Abstract: The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.

Abstract: The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.

Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.

Abstract: A semiconductor chip assembly includes a semiconductor chip and a pyrolytic graphite element that is an electrode that is electrically connected to and provides electrical conduction of current from the chip during operation of the chip.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.