Patents by Inventor Ford B. Grigg
Ford B. Grigg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8455983Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.Type: GrantFiled: November 22, 2011Date of Patent: June 4, 2013Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Ed A. Schrock, Ford B. Grigg
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Publication number: 20120070959Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.Type: ApplicationFiled: November 22, 2011Publication date: March 22, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Alan G. Wood, Ed A. Schrock, Ford B. Grigg
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Patent number: 8062958Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.Type: GrantFiled: April 1, 2009Date of Patent: November 22, 2011Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Ed A. Schrock, Ford B. Grigg
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Patent number: 7811903Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive back side silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.Type: GrantFiled: October 25, 2007Date of Patent: October 12, 2010Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, Timothy L. Jackson
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Publication number: 20100252915Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.Type: ApplicationFiled: April 1, 2009Publication date: October 7, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Alan G. Wood, Ed A. Schrock, Ford B. Grigg
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Patent number: 7557452Abstract: A conductive structure configured to connect a contact pad of a semiconductor device with a corresponding contact pad of a substrate. The conductive structure includes two interconnectable members, one securable to each of the corresponding contact pads. Each member includes a dielectric jacket having an aperture that laterally confines conductive material of a conductive center thereof over the contact pad to which the member is secured. The conductive center of a female member of the conductive structure only partially fills the aperture of the jacket thereof so as to form a receptacle for an end of the male member of the conductive structure. One or both of the male and female members may also be configured to limit the insertion of the male member into the receptacle of the female member. The members of the conductive structure may be preformed structures which are attached to a surface of a semiconductor device or other substrate.Type: GrantFiled: June 8, 2000Date of Patent: July 7, 2009Assignee: Micron Technology, Inc.Inventors: Vernon M. Williams, Ford B. Grigg, Bret K. Street
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Patent number: 7291543Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive back side silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.Type: GrantFiled: June 1, 2005Date of Patent: November 6, 2007Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, Timothy L. Jackson
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Patent number: 7189600Abstract: Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to be secured to other semiconductor device components, are fabricated under control of a program. The stiffeners may be formed by selectively depositing or consolidating unconsolidated material. They may include a plurality of mutually adhered regions. The stiffeners may be configured to prevent torsional flexion or bending of the connective structure to which they are to be secured, to reinforce sprocket or indexing holes in connective structures or to include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude.Type: GrantFiled: January 25, 2006Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7170171Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or otherwise disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.Type: GrantFiled: March 9, 2005Date of Patent: January 30, 2007Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7138724Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured with corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.Type: GrantFiled: October 17, 2003Date of Patent: November 21, 2006Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, William J. Reeder
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Patent number: 7134390Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.Type: GrantFiled: June 26, 2003Date of Patent: November 14, 2006Assignee: Micron Technology, Inc.Inventors: Chad Cobbley, Ford B. Grigg
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Patent number: 7125748Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured with corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.Type: GrantFiled: April 8, 2005Date of Patent: October 24, 2006Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, William J. Reeder
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Patent number: 7122905Abstract: Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed circuit boards. One embodiment can include a die, an interposer substrate, a solder-ball, and a dielectric compound. The die can have an integrated circuit and at least one bond-pad coupled to the integrated circuit. The interposer substrate is coupled to the die and can have at least one ball-pad electrically coupled to the bond-pad on the die. The interposer substrate can also have a trace line adjacent to the ball-pad, and a solder-mask having an opening over the ball-pad. The solder-ball can contact the ball-pad in the opening. The dielectric compound can insulate the ball-pad and the solder-ball from an exposed portion of the adjacent trace line in the opening.Type: GrantFiled: July 15, 2003Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7115981Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.Type: GrantFiled: October 7, 2003Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7109106Abstract: Methods of fabricating and disposing supports around contact pads of semiconductor device components and other substrates include use of stereolithographic techniques. The supports may be preformed structures which are attached to a surface of a semiconductor device component or other substrate. Alternatively, the supports may be fabricated on the surface of the semiconductor device or other substrate. One or more of the supports may be positioned around the contact pads of a semiconductor device component or other substrate before or after solder balls are secured to the contact pads. Upon reflowing the solder balls to connect the semiconductor device face-down to a higher level substrate, the supports prevent the reflowed solder from contacting regions of the surface of the semiconductor device that surround the contact pads thereof.Type: GrantFiled: April 14, 2003Date of Patent: September 19, 2006Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7064002Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.Type: GrantFiled: November 21, 2002Date of Patent: June 20, 2006Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7041532Abstract: A method for fabricating an interposer includes providing an interposer substrate with at least one slot or aperture therethrough and forming at least one upwardly protruding dam on the interposer substrate, adjacent to the slot or aperture. The upwardly protruding dam or dams may at least partially surround the slot or aperture. Accordingly, the upwardly protruding dam or dams may laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. Programmed material consolidation processes, such as stereolithography, may be used to form the at least one upwardly protruding dam.Type: GrantFiled: February 25, 2004Date of Patent: May 9, 2006Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7029954Abstract: Stiffeners for tapes, films, or other connective structures, which are configured to be secured to a semiconductor device component, such as a semiconductor die or substrate, by tape-automated bonding processes, are fabricated by stereolithographic processes and may include one or two or more layers. The stiffeners are configured to prevent torsional flexion or bending of the connective structure to which they are to be secured. The stiffeners may reinforce sprocket or indexing holes in connective structures. The stiffeners may include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude. The stereolithographic method for fabricating stiffeners may include use of a machine vision system that recognizes the position and orientation of one or more connective structures on which at least an element of each of the stiffeners is to be fabricated so that the application of material thereto may be controlled.Type: GrantFiled: June 8, 2004Date of Patent: April 18, 2006Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 6984545Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned between bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured and corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is then attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are then used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.Type: GrantFiled: July 22, 2002Date of Patent: January 10, 2006Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, William J. Reeder
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Patent number: 6979888Abstract: A semiconductor device assembly having a lead frame and a semiconductor die configured to be attached to each other is disclosed. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor die is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.Type: GrantFiled: December 28, 2001Date of Patent: December 27, 2005Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, Warren M. Farnworth