Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive backside silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract: Dielectric rings to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the rings on semiconductor devices and other substrates. Semiconductor devices including the rings and having contact pads exposed through the rings are also disclosed. One or more of the rings are disposed around the contact pads of a semiconductor device or other substrate before or after solder balls are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures which are attached to a surface of a semiconductor device or other substrate.

Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive backside silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographicaily formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive backside silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing, and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor die configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor die is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: The invention includes a semiconductor processing method of forming a die package. An insulative substrate is provided. Circuitry is over a topside of the substrate, and a slit extends through the substrate. A semiconductive-material-comprising die is provided beneath the substrate, and has a surface exposed through the slit in the substrate. The die has an edge. There is a gap between the die and an underside of the substrate. A radiation-curable material is injected through this slit and into the gap. Radiation is directed from over the edge to the gap to cure at least a portion of the radiation-curable material within the gap and thus form a dam which impedes non-cured radiation-curable material from flowing beyond the edge.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: Dielectric rings to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the rings on semiconductor devices and other substrates. One or more of the rings may be positioned around the contact pads of a semiconductor device or other substrate before or after solder balls are secured to the contact pads. Upon reflowing the solder balls to connect the semiconductor device face-down to a higher level substrate, the rings prevent the reflowed solder from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures which are attached to a surface of a semiconductor device or other substrate. Alternatively, the rings can be fabricated on the surface of the semiconductor device or other substrate. A stereolithographic method of fabricating the rings is disclosed.

Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed.

Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When the marking is formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package structure. The marking may be formed as apertures through or recessed areas in one or more stereolithographically fabricated layers of material. Alternatively, the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. The marking may be formed directly on a surface of a packaged or bare semiconductor device component. As an alternative, the marking can be fabricated separately from a semiconductor device component, then secured thereto. Methods of stereolithographically marking semiconductor device components are also disclosed.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When the marking is formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package structure. The marking may be formed as apertures through or recessed areas in one or more stereolithographically fabricated layers of material. Alternatively, the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. The marking may be formed directly on a surface of a packaged or bare semiconductor device component. As an alternative, the marking can be fabricated separately from a semiconductor device component, then secured thereto. Methods of stereolithographically marking semiconductor device components are also disclosed.

Abstract: Stiffeners for tapes, films, or other connective structures that are configured to be secured to a semiconductor device component, such as a semiconductor die or substrate, by tape-automated bonding processes. The stiffeners are fabricated by stereolithographic processes and may include one or two more layers. The stiffeners are configured to prevent torsional flexion or bending of the connective structure to which they to be secured. The stiffeners may reinforce sprocket or indexing holes in connective structures. The stiffeners may include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude. The stereolithographic method for fabricating stiffeners may include use of a machine vision system that recognizes the position and orientation of one or more connective structures on which at least an element of each of the stiffeners is to be fabricated so that the application of material thereto may be controlled.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.