Patents by Inventor Ford B. Grigg

Ford B. Grigg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010038144
    Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.
    Type: Application
    Filed: May 24, 2001
    Publication date: November 8, 2001
    Inventor: Ford B. Grigg
  • Publication number: 20010035597
    Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed.
    Type: Application
    Filed: December 14, 2000
    Publication date: November 1, 2001
    Inventors: Ford B. Grigg, James M. Ocker, Rick A. Leininger
  • Publication number: 20010012641
    Abstract: In one aspect, the invention encompasses a semiconductor processing method. An insulative substrate is provided. Such substrate has an opening extending therethrough. A semiconductor-material-comprising die is provided adjacent to the substrate, and the die has an edge. A gap is between the die and substrate, and exposed through the opening. A liquid radiation-curable material is flowed through the opening and into the gap. Radiation is directed from beside the die to cure at least a portion of the radiation-curable material within the gap and thus form a dam which impedes non-cured radiation-curable material from flowing beyond the edge. In another aspect, the invention encompasses a method of forming a die package. An insulative substrate is provided. Circuitry is over a topside of the substrate, and a slit extends through the substrate. A semiconductive-material-comprising die is provided beneath the substrate, and has a surface exposed through the slit in the substrate. The die has an edge.
    Type: Application
    Filed: July 26, 1999
    Publication date: August 9, 2001
    Inventors: FORD B. GRIGG, JOSEPH M. BRAND
  • Patent number: 6269742
    Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: August 7, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Chad Cobbley, Ford B. Grigg
  • Publication number: 20010007784
    Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.
    Type: Application
    Filed: February 28, 2001
    Publication date: July 12, 2001
    Inventors: Ford B. Grigg, Warren M. Farnworth
  • Patent number: 6248611
    Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, Warren M. Farnworth
  • Patent number: 6089151
    Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: July 18, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Chad Cobbley, Ford B. Grigg
  • Patent number: 5981102
    Abstract: In accordance with one aspect of the invention, a thin profile battery apparatus comprises at least two thin profile batteries conductively bonded to one another, with one of the batteries including portion which overhangs the other. In one implementation, the batteries comprise button type batteries. In one implementation, the two thin profile batteries are the same size and shape. In accordance with another aspect, a radio frequency communication device comprises a substrate having conductive paths including an antenna. At least one integrated circuit chip is mounted to the substrate and in electrical connection with a first portion of the substrate conductive paths. At least two thin profile batteries conductively bonded in series with and over one another and a second portion of the substrate conductive paths are included. One of the batteries has a portion which overhangs the other and is in electrical connection with a third portion of the substrate conductive paths.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: November 9, 1999
    Assignee: Micron Communications, Inc.
    Inventors: Ford B. Grigg, Rickie C. Lake
  • Patent number: 5959347
    Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: September 28, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, Warren M. Farnworth
  • Patent number: 5840598
    Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: November 24, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, Warren M. Farnworth