Patents by Inventor François Roy

François Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190308099
    Abstract: Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 10, 2019
    Inventors: Paul Lalonde, Paul Leventis, Jean-Francois Roy
  • Publication number: 20190312170
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Application
    Filed: December 17, 2018
    Publication date: October 10, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • Patent number: 10421315
    Abstract: The invention relates to a device for tensioning a canvas on a frame, which is for assembling two bars the ends of which comprise a groove. The device comprises: an optional sheath intended to be immobilized in a groove; a spacer comprising a central portion from which extend two lateral portions each having a bearing face coming to abut against the bottom of the sheath; a tensioner comprising a central portion from which extend securing means for securing the tensioner to the bars, via the sheath; a connecting member for connecting the spacer to the tensioner, and means for bringing the spacer closer to the tensioner, wherein the spacer being brought closer to the tensioner will cause each bar to translate along its longitudinal axis so as to space the bars apart from each other while keeping them perpendicular to each other.
    Type: Grant
    Filed: October 28, 2017
    Date of Patent: September 24, 2019
    Inventor: Francois Roy
  • Publication number: 20190280024
    Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Publication number: 20190239806
    Abstract: It is described a system and a method for respiratory activity analysis comprising the use of Respiratory Inductance Plethysmography (RIP). In particular, a wearable system for extracting physiological parameters of a person by measuring at least one plethysmographic signal is disclosed. The system comprises: a wearable garment fitting a body part of the person; at least one wire supported by or embedded into the garment, each wire forming a loop around the body part when the person wears the garment for measuring a plethysmographic signal; and an electronic device supported by or fixed on the garment and including a Colpitts oscillator connected to each wire loop, wherein the Colpitts oscillator has an optimal frequency band from 1 MHz to 15 MHz for extracting the plethysmographic signal measured by each wire, the electronic device converting analog information measured by the Colpitts oscillator into digital analyzable information.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Jean-Francois ROY, Pierre-Alexandre FOURNIER, Charles ROBILLARD, Robert CORRIVEAU, Simon DUBEAU, Antoine GAGNE-TURCOTTE, David KHOUYA
  • Publication number: 20190237499
    Abstract: In an embodiment, an image sensor includes a semiconductor region, a first doped region disposed over the semiconductor region, a ring shaped well disposed over the first doped region and surrounding parts of the first doped region, a second doped region formed within the ring shaped well and disposed over the first doped region, and a third doped region disposed over the second doped region. The ring shaped well is defined by a conductor surrounded by an insulator. The conductor is connected to a voltage terminal. The third doped region is more heavily doped than the second doped region, which is more heavily doped than the first region, and are all of the same doping type. The first doped region and the second doped region within the ring shaped well, form a potential barrier for controlling transfer of charge carriers from the first doped region to the third doped region.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventor: Francois Roy
  • Patent number: 10362250
    Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Guyader, Francois Roy
  • Patent number: 10361238
    Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10355041
    Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10324870
    Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 18, 2019
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 10326767
    Abstract: Disclosed is a system for a facility supporting an access controller, at least one ingress card reader and an auto-enrollment type controller including a front panel having a single button, a controller board, a terminal block for connecting at least the one ingress card reader to the auto-enrollment type controller board and to connect the auto-enrollment type controller to door locks, and a mounting plate, with the auto-enrollment type controller being configured by a user according to operational requirements of the facility by the user asserting the button for a defined period of time.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 18, 2019
    Assignee: SENSORMATIC ELECTRONICS, LLC
    Inventors: Stephan Frenette, Gabriel Labrecque, Jean-Francois Roy
  • Publication number: 20190181176
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois ROY, Sonarith CHHUN
  • Publication number: 20190181180
    Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10321073
    Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Publication number: 20190137609
    Abstract: A sensor array includes pixel kernels, wherein each pixel kernel includes RGB pixels, the RGB pixels being configured to provide a plurality of color signals, and Z pixels each having a single memory element, the Z pixels being configured to provide a single TOF signal. Each pixel kernel includes two to four Z pixels. The RGB and Z pixels can be integrated together on a single sensor array.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 9, 2019
    Inventor: Francois Roy
  • Publication number: 20190086519
    Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Boris Rodrigues Goncalves, Marie Guillon, Yvon Cazaux, Benoit Giffard
  • Patent number: 10199409
    Abstract: A semiconductor device includes a first semiconductor substrate with a first transistor therein. The first transistor includes a first source-drain formed by a doped region in the first semiconductor substrate. An intermediary insulating layer is formed on and above the first semiconductor substrate. A second semiconductor substrate is formed on and above the intermediary insulating layer. A second transistor is formed in the second semiconductor substrate, and includes a second source-drain formed by a doped region in the second semiconductor substrate. A trench is formed in the second semiconductor substrate and in contact with the doped region for the second semiconductor substrate. The trench has a thickness equal to that of the second semiconductor substrate. Metal wiring extends from a contact with the doped region for the first source-drain, through the intermediary insulating layer and the trench, to make electrical contact with the doped region for the second source-drain.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10193009
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10192917
    Abstract: A photosensor is formed within a semiconductor substrate layer having a front side and a back side. An isolation structure delimits an active region of the semiconductor substrate layer which includes a charge collecting region. The front side of semiconductor substrate layer includes a charge transfer circuit. A reflecting mirror is mounted at the back side of the semiconductor substrate layer. The reflecting mirror includes a pupil opening configured to admit light into the active region at the back side. An underside reflective surface of the reflecting mirror is configured to reflect light received from the active region back into the active region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Bastien Mamdy
  • Publication number: 20190027523
    Abstract: An electronic image capture device includes a first portion and a second portion. The first portion is formed by a substrate wafer provided on one side with electronic circuits and a dielectric layer with a network of electrical connections and external electrical contacts on an outer surface. The second portion includes a pixel wafer capable of generating electrical signals under the effect of light, a substrate wafer mounted to the pixel wafer and provided with electronic circuits and a dielectric layer with a network of electrical connections and external electrical contacts on an outer surface. The outer surfaces and external electrical contacts are bonded to each other so as to mount the first portion to the second portion. A connection pad extends through a hole in the pixel wafer to make electrical connection to the network of electrical connections of the second portion.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY