Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A method is provided for suppressing a transient signal (VTR) using a single semiconductor die (130). The method comprises the step of loading the transient signal with first and second junctions (110, 112) formed adjacent to a first doped region (140) of the semiconductor die. The first junction breaks down to generate a current while the second junction forward biases to route the current across an undepleted portion (161) of the first doped region and through the second junction.

Abstract: A semiconductor device (10) having a termination structure (25) and a reduced on-resistance. The termination structure (25) is fabricated using the same processing steps that were used for manufacturing an active device region (21). The termination structure (25) and the active device region (21) are formed by etching trenches (22, 23) into a drift layer (14). The trenches (22, 23) are filled with a doped polysilicon trench fill material (24), which is subsequently planarized. The semiconductor device (10) is formed in the trenches (22) filled with the polysilicon trench fill material (24) that are in the active region. The trenches (23) filled with the polysilicon trench fill material (24) in a termination region serve as termination structures.

Abstract: A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.

Abstract: A method of forming an alloyed drain field effect transistor (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride (17) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Abstract: A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.

Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Abstract: A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

Abstract: Filled trenches useful in semiconductor devices for isolation or other purposes are provided by etching a trench in the semiconductor substrate, lining the trench with a first material (e.g., silicon dioxide), covering the first material with a seed layer (e.g., polysilicon) for nucleating a further material, removing a part of the seed layer on the first material in an upper part of the trench, and then filling the trench by selectively depositing the further material (e.g., polysilicon) on the remaining seed layer.Thermally grown silicon dioxide is convenient for the first material. The first material and seed layer may extend over the substrate surface. The upper portion of the seed layer is conveniently removed by first covering the seed layer with a mask (e.g., photoresist) and then etching back the mask to expose the seed layer above the substrate surface and in the upper portion of the trench, leaving part of the mask in the lower portion of the trench.

Abstract: Maskless etching of polysilicon is accomplished by exposing portions of a polysilicon surface to ion bombardment. Bombardment by oxygen or hydrogen ions is effective to reduce the etch rate of polysilicon in a chlorine-containing plasma. Therefore, patterned ion bombardment prior to etching in a chlorine plasma is effective to pattern the polysilicon surface.

Abstract: A method is provided for anisotropically etching organic material to reduce mask undercutting. The layer of organic material to be patterned, with an overlying patterning mask is provided on a substrate. The substrate with the layer of organic material on it is placed on the powered electrode within a plasma reactor. A hydrogen plasma is generated in the reactor at a pressure between about 13.3 Pa and about 53 Pa. The organic layer which is not protected by the etch mask is etched by the hydrogen plasma. At these pressures the organic layer is removed by a process of ion assisted etching in which the hydrogen plasma chemically reacts with the organic material and the reaction is enhanced by ionic bombardment of the plasma species. Because the substrate and the organic material are placed on the powered electrode, the plasma ions impact the surface of the organic layer in a direction substantially perpendicular to the surface of the layer thus providing anisotropy to the etch.