Abstract: The present invention discloses a method for assaying the binding of L104EA29YIg to a receptor. The receptor is preferably CD86 or CD80. The present invention also discloses antibodies to be used in the assay, as well as hybridomas expressing the antibodies.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.

Abstract: A method of fabricating on a substrate an optical detector in an optical waveguide, the method involving: forming at least one layer on a surface of the substrate, said at least one layer comprising SiGe; implanting an impurity into the at least one layer over a first area to form a detector region for the optical detector; etching into the at least one layer in a first region and a second region to form a ridge between the first and second regions, said ridge defining the optical detector and the optical waveguide; filling the first and second regions with a dielectric material having a lower refractive index than SiGe; and after filling the first and second regions with the dielectric material, removing surface material to form a planarized upper surface.

Abstract: Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process.

Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.

Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.

Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.

Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Abstract: Porous and/or curved nanofiber bearing substrate materials are provided having enhanced surface area for a variety of applications including as electrical substrates, semipermeable membranes and barriers, structural lattices for tissue culturing and for composite materials, production of long unbranched nanofibers, and the like.

Abstract: Porous and/or curved nanofiber bearing substrate materials are provided having enhanced surface area for a variety of applications including as electrical substrates, semipermeable membranes and barriers, structural lattices for tissue culturing and for composite materials, production of long unbranched nanofibers, and the like.

Abstract: The present invention relates to methods of vaccinating subjects receiving immune modulating therapy, such as soluble CTLA4 molecules, for treatment of immune system diseases mediated by T-cell interactions with B7-positive cells including, but not limited to, autoimmune diseases, immunoproliferative diseases, and immune disorders associated with graft transplantation.

Abstract: The present invention discloses a method for assaying the binding of L104EA29YIg to a receptor. The receptor is preferably CD86 or CD80. The present invention also discloses antibodies to be used in the assay, as well as hybridomas expressing the antibodies.

Abstract: The present invention is directed to a peripherally pivoted oscillating vane machine (OVM). The OVM has been optimized for performance and efficiency. This has been accomplished by reducing loads on the drive mechanism and by employing de-phased motion of the peripherally pivoted vanes in conjunction with improved porting configurations as well as valve actuation and manufacture.

Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.

Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.

Abstract: A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.