Patents by Inventor Francisco A. Leon
Francisco A. Leon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080150003Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: Jian Chen, Xiangfeng Duan, Karen Cruden, Chao Liu, Madhuri L. Nallabolu, Srikanth Ranganathan, Francisco Leon, J. Wallace Parce
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Publication number: 20080150004Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.Type: ApplicationFiled: March 19, 2007Publication date: June 26, 2008Applicant: NANOSYS, INC.Inventors: Jian Chen, Xiangfeng Duan, Karen Cruden, Chao Liu, Madhuri L. Nallabolu, Srikanth Ranganathan, Francisco Leon, J. Wallace Parce
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Publication number: 20080128688Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed.Type: ApplicationFiled: January 18, 2008Publication date: June 5, 2008Applicant: NANOSYS, INC.Inventors: Yaoling Pan, Francisco Leon, David P. Stumbo
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Patent number: 7365395Abstract: Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric constants can be achieved with an artificial dielectric using nanostructures. The dielectric constant can be adjusted by varying the length, diameter, carrier density, shape, aspect ratio, orientation and density of the nanostructures. Additionally, a controllable artificial dielectric using nanostructures, such as nanowires, is disclosed in which the dielectric constant can be dynamically adjusted by applying an electric field to the controllable artificial dielectric. A wide range of electronic devices can use artificial dielectrics with nanostructures to improve performance.Type: GrantFiled: August 15, 2005Date of Patent: April 29, 2008Assignee: Nanosys, Inc.Inventors: David P. Stumbo, Stephen A. Empedocles, Francisco Leon, J. Wallace Parce
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Patent number: 7345307Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed.Type: GrantFiled: September 22, 2005Date of Patent: March 18, 2008Assignee: Nanosys, Inc.Inventors: Yaoling Pan, Francisco Leon, David P. Stumbo
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Publication number: 20080029757Abstract: A semiconductor device including: a quantum well having photon emission energy level, the quantum well having at least one active layer and two barrier layers, one disposed above the active layer and one disposed below the active layer; and injection regions for injecting electrons into the quantum well, wherein the electrons are cool electrons with respect to the active layer of the quantum well.Type: ApplicationFiled: November 14, 2006Publication date: February 7, 2008Applicant: Applied Materials, Inc.Inventors: Lawrence West, Francisco Leon
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Publication number: 20080032134Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.Type: ApplicationFiled: February 13, 2007Publication date: February 7, 2008Applicant: NANOSYS, Inc.Inventors: Jeffery Whiteford, Rhett Brewer, Mihai Buretea, Jian Chen, Karen Cruden, Xiangfeng Duan, William Freeman, David Heald, Francisco Leon, Chao Liu, Andreas Meisel, Kyu Min, J. Parce, Erik Scher
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Publication number: 20080019999Abstract: The present invention relates to methods of vaccinating subjects receiving immune modulating therapy, such as soluble CTLA4 molecules, for treatment of immune system diseases mediated by T-cell interactions with B7-positive cells including, but not limited to, autoimmune diseases, immunoproliferative diseases, and immune disorders associated with graft transplantation.Type: ApplicationFiled: May 8, 2007Publication date: January 24, 2008Inventors: George Vratsanos, Francisco Leon, Lee Tay, Kenneth Bahrt
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Publication number: 20070296032Abstract: Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric constants can be achieved with an artificial dielectric using nanostructures. The dielectric constant can be adjusted by varying the length, diameter, carrier density, shape, aspect ratio, orientation and density of the nanostructures. Additionally, a controllable artificial dielectric using nanostructures, such as nanowires, is disclosed in which the dielectric constant can be dynamically adjusted by applying an electric field to the controllable artificial dielectric. A wide range of electronic devices can use artificial dielectrics with nanostructures to improve performance.Type: ApplicationFiled: August 15, 2005Publication date: December 27, 2007Applicant: Nanosys, Inc.Inventors: David Stumbo, Stephen Empedocles, Francisco Leon, J. Parce
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Publication number: 20070272996Abstract: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.Type: ApplicationFiled: April 13, 2007Publication date: November 29, 2007Applicant: Applied Materials, Inc.Inventors: Francisco Leon, Lawrence West
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Publication number: 20070172895Abstract: The present invention discloses a method for assaying the binding of L104EA29YIg to a receptor. The receptor is preferably CD86 or CD80. The present invention also discloses antibodies to be used in the assay, as well as hybridomas expressing the antibodies.Type: ApplicationFiled: January 22, 2007Publication date: July 26, 2007Inventors: Catherine Fleener, Robert Townsend, Francisco Leon
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Patent number: 7205624Abstract: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.Type: GrantFiled: October 6, 2004Date of Patent: April 17, 2007Assignee: Applied Materials, Inc.Inventors: Francisco A. Leon, Lawrence C. West
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Publication number: 20070053643Abstract: A method of fabricating on a substrate an optical detector in an optical waveguide, the method involving: forming at least one layer on a surface of the substrate, said at least one layer comprising SiGe; implanting an impurity into the at least one layer over a first area to form a detector region for the optical detector; etching into the at least one layer in a first region and a second region to form a ridge between the first and second regions, said ridge defining the optical detector and the optical waveguide; filling the first and second regions with a dielectric material having a lower refractive index than SiGe; and after filling the first and second regions with the dielectric material, removing surface material to form a planarized upper surface.Type: ApplicationFiled: August 31, 2006Publication date: March 8, 2007Applicant: Applied Materials, Inc.Inventors: Lawrence West, Gregory Wojcik, Francisco Leon, Yonah Cho, Andreas Goebel
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Publication number: 20070018270Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.Type: ApplicationFiled: July 10, 2006Publication date: January 25, 2007Applicant: Applied Materials, Inc.Inventors: Francisco Leon, Lawrence West, Yuichi Wada, Gregory Wojcik, Stephen Moffatt
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Patent number: 7151881Abstract: An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.Type: GrantFiled: May 28, 2004Date of Patent: December 19, 2006Assignee: Applied Materials, Inc.Inventors: Lawrence C. West, Thomas P. Pearsall, Francisco A. Leon, Stephen Moffatt
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Publication number: 20060214156Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed.Type: ApplicationFiled: September 22, 2005Publication date: September 28, 2006Applicant: Nanosys, Inc.Inventors: Yaoling Pan, Francisco Leon, David Stumbo
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Patent number: 7101725Abstract: A method of fabricating on optical detector, the method including providing a substrate that includes an optical waveguide formed therein and having a surface for fabricating microelectronic circuitry thereon; fabricating microelectronic circuitry on the substrate, the fabricating involving a plurality of sequential process phases; after a selected one of the plurality of sequential process phases has occurred and before the next process phase after the selected one of the plurality of process phases begins, fabricating an optical detector within the optical waveguide; and after fabricating the optical detector in the waveguide, completing the plurality of sequential process phases for fabricating the microelectronic circuitry.Type: GrantFiled: July 22, 2004Date of Patent: September 5, 2006Assignee: Applied Materials, Inc.Inventors: Yuichi Wada, Francisco A. Leon
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Patent number: 7075165Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.Type: GrantFiled: May 28, 2004Date of Patent: July 11, 2006Assignee: Applied Material, Inc.Inventors: Francisco A. Leon, Lawrence C. West, Yuichi Wada, Gregory L. Wojcik, Stephen Moffatt
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Publication number: 20060081886Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.Type: ApplicationFiled: September 22, 2005Publication date: April 20, 2006Applicant: Nanosys, Inc.Inventors: Shahriar Mostarshed, Jian Chen, Francisco Leon, Yaoling Pan, Linda Romano
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Publication number: 20060040103Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.Type: ApplicationFiled: June 7, 2005Publication date: February 23, 2006Applicant: NANOSYS, Inc.Inventors: Jeffery Whiteford, Rhett Brewer, Mihai Buretea, Jian Chen, Karen Cruden, Xiangfeng Duan, William Freeman, David Heald, Francisco Leon, Chao Liu, Andreas Meisel, Kyu Min, J. Parce, Erik Scher