Patents by Inventor Francisco A. Leon

Francisco A. Leon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7001788
    Abstract: A method of fabricating a waveguide mirror that involves etching a trench in a silicon substrate; depositing a film (e.g. silicon dioxide) over the surface of the silicon substrate and into the trench; ion etching the film to remove at least some of the deposited silicon dioxide and to leave a facet of film in inside corners of the trench; depositing a layer of SiGe over the substrate to fill up the trench; and planarizing the deposited SiGe to remove the SiGe from above the level of the trench.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 21, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Francisco A. Leon, Lawrence C. West, Gregory L. Wojcik, Yuichi Wada
  • Publication number: 20050212068
    Abstract: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
    Type: Application
    Filed: October 6, 2004
    Publication date: September 29, 2005
    Applicant: Applied Materials, Inc.
    Inventors: Francisco Leon, Lawrence West
  • Publication number: 20050214964
    Abstract: An optical detector including a substrate; an island of detector material formed on the substrate, the island being a stack extending up from the substrate of alternating layers of first and second semiconductor materials, the island having a horizontally oriented top end, a vertically oriented first sidewall, and vertically oriented second sidewall that is opposite the first sidewall, the island having a first doped region extending into the island through first sidewall and forming a first conductive region that extends down into the island of detector material, the island also having a second doped region extending into the island through the second sidewall and forming a second conductive region that extends down into island of the detector material, the first and second conductive regions each having a top end that is part of the top end of the island; a first electrical connection to the top end of the first conductive region; and a second electrical connection to the top end of the second conductive re
    Type: Application
    Filed: October 6, 2004
    Publication date: September 29, 2005
    Applicant: Applied Materials, Inc. PATENT COUNSEL, Legal Affairs Dept.
    Inventors: Lawrence West, Francisco Leon
  • Patent number: 6898781
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Publication number: 20050054130
    Abstract: A method of fabricating a waveguide mirror that involves etching a trench in a silicon substrate; depositing a film (e.g. silicon dioxide) over the surface of the silicon substrate and into the trench; ion etching the film to remove at least some of the deposited silicon dioxide and to leave a facet of film in inside corners of the trench; depositing a layer of SiGe over the substrate to fill up the trench; and planarizing the deposited SiGe to remove the SiGe from above the level of the trench.
    Type: Application
    Filed: May 28, 2004
    Publication date: March 10, 2005
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Francisco Leon, Lawrence West, Gregory Wojcik, Yuichi Wada
  • Publication number: 20050054131
    Abstract: A method of fabricating on optical detector, the method including providing a substrate that includes an optical waveguide formed therein and having a surface for fabricating microelectronic circuitry thereon; fabricating microelectronic circuitry on the substrate, the fabricating involving a plurality of sequential process phases; after a selected one of the plurality of sequential process phases has occurred and before the next process phase after the selected one of the plurality of process phases begins, fabricating an optical detector within the optical waveguide; and after fabricating the optical detector in the waveguide, completing the plurality of sequential process phases for fabricating the microelectronic circuitry.
    Type: Application
    Filed: July 22, 2004
    Publication date: March 10, 2005
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Yuichi Wada, Francisco Leon
  • Publication number: 20050051767
    Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
    Type: Application
    Filed: May 28, 2004
    Publication date: March 10, 2005
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Francisco Leon, Lawrence West, Yuichi Wada, Gregory Wojcik, Stephen Moffatt
  • Publication number: 20050053347
    Abstract: An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.
    Type: Application
    Filed: May 28, 2004
    Publication date: March 10, 2005
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Lawrence West, Thomas Pearsall, Francisco Leon, Stephen Moffatt
  • Patent number: 6818559
    Abstract: Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: Francisco A. Leon, Everett X. Wang
  • Patent number: 6730988
    Abstract: Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: Francisco A. Leon, Everett X. Wang
  • Publication number: 20040025140
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Application
    Filed: July 30, 2003
    Publication date: February 5, 2004
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Patent number: 6625802
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Publication number: 20030149956
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 7, 2003
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Publication number: 20030136760
    Abstract: Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 24, 2003
    Inventors: Francisco A. Leon, Everett X. Wang
  • Publication number: 20020137247
    Abstract: Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.
    Type: Application
    Filed: March 21, 2001
    Publication date: September 26, 2002
    Inventors: Francisco A. Leon, Everett X. Wang
  • Patent number: 6103429
    Abstract: A technique for fabricating a phase shift mask with multiple phase shifts by using self-aligned spacers to form phase shifting regions on a surface of a mask substrate. Three phase shifting regions are formed corresponding to 180.degree./120.degree./60.degree. phase shifts or delays on the surface of mask substrate. The three phase shifting regions are fabricated from three different dielectric materials, each having a different refractive indices. The first phase shifting region is formed by a photolithography technique, but the other two phase shifting regions are formed by the formation of self-aligned spacers. In an alternative technique, all three of the phase shifting regions are formed by the use of self-aligned spacers.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: August 15, 2000
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Francisco A. Leon, Richard Elliot Schenker
  • Patent number: 5644688
    Abstract: A method for simulating changes to the topography of a workpiece, e.g. a semiconductor wafer, as it undergoes process steps. The method may be used to simulated isotropic or anisotropic deposition or etch process steps. A solids modeling system is used to define and deform material solids. Material solids represent the different materials on a workpiece. A plurality of trajectory solids are constructed to cause the deformation of the material solids. Deformation of a material solid is accomplished through the performance of boolean operations between the material solid and one or more trajectory solids. A characteristic of a trajectory solid, e.g. a radius or height, relates to the rate of etch or deposition for the particular process step. The method of construction of trajectory solids in the present invention enables simulation of spatially varying process steps, avoids the creation of invalid self-intersecting surfaces and minimizes the creation of small edges that lead to irregular surfaces.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: July 1, 1997
    Inventors: Francisco A. Leon, Satoshi Tazawa, Gregory Anderson
  • Patent number: 5586230
    Abstract: A method for deforming a solid and avoiding the creation of self-intersecting solid structures in a topography simulator. In a topography simulated based on a solids modeling system, self-intersecting structures are solids which have boundaries that intersect. Such self-intersecting structures are invalid and cannot be processed. A general method for sweeping a solid surface to create a deformed solid and avoid the creation of self-intersecting solid structures is described, which include the steps of: providing a material solid with a surface represented as one or more segments; constructing a first segment solid for a first segment; performing a boolean set operation between the solid being swept and the first segment solid creating a temporary first solid; identifying a second segment; constructing a second segment solid for the second segment; and performing the boolean set operation between said temporary first solid and said first segment solid creating said deformed first solid.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: December 17, 1996
    Assignees: Intel Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Francisco A. Leon, Satoshi Tazawa
  • Patent number: 5416729
    Abstract: A topography simulator using a "Generalized Solid Modeling (GSM) method" to simulate isotropic or anisotropic deposition and etch process steps on a workpiece. A solids modeling system that utilizes a boundary representation model for representing material object solids provides a basis for the topography simulator. A workpiece in the model is comprised of a collection of material solids. The present invention provides for accurately representing the interfaces of different material solids. The airspace above the top surface material is defined as an air solid. Boolean set operations between the various material solids and the air solid are performed to deform the wafer topography. The present invention further provides means for simulating an etch process step at the interface of materials with different etch rates.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: May 16, 1995
    Assignees: Nippon Telegraph and Telephone Corporation, Intel Corporation
    Inventors: Francisco A. Leon, Donald L. Scharfetter, Gregory Anderson, Satoshi Tazawa, Akira Yoshii
  • Patent number: 5379225
    Abstract: A method for efficient calculation of the movement of a vertex in a three-dimensional topography simulator. The method is particularly well suited for calculating vertex movement for cases in which an etch/deposition rate depends on the angle between the surface normal and the vertical direction. A workpiece is represented as a collection of material solids. Each of the material solids has a boundary model representation, which include vertices, edges and faces. The method of the present invention generally includes the steps of: identifying a first plane, a second plane and a third plane that approximate all the planes that are adjacent to a vertex point to be moved; determining a first observation vector; creating a set of advanced virtual planes; identifying a second observation vector; determining the furthest intersection point of one of the planes in the set of advanced planes and the second observation vector; and moving the vertex to the point identified in the prior step.
    Type: Grant
    Filed: June 24, 1992
    Date of Patent: January 3, 1995
    Assignees: Intel Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Satoshi Tazawa, Francisco A. Leon, Donald L. Sharfetter, Kazuyuki Saito, Akira Yoshii