Abstract: System and method to localize a position of an RRAM filament of resistive memory device at very low bias voltages using a scanning laser beam. The approach is non-invasive and allows measurement of a large number of devices for creating statistics relating to the filament formation. A laser microscope system is configured to perform a biasing the RRAM cell with voltage (or current). Concurrent to the applied bias, a laser beam is generated and aimed at different positions of the RRAM cell (e.g., by a raster scanning). Changes in the current (or voltage) flowing through the cell are measured. The method creates a map of the current (or voltage) changes at the different laser positions and detects a spot in the map corresponding to higher (or lower) current (or voltage). The method determines the (x,y) position of the spot compared to the edge/center of the RRAM cell.

Abstract: Techniques regarding autonomous identification of aged circuits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an identification component, operatively coupled to the processor, that can identify an aged circuit by analyzing a current-voltage characteristic curve for a distortion in a sub-threshold quiescent current signature of the aged circuit.

Abstract: A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.

Abstract: A physical unclonable function device includes alternating regions of programable material and electrically conductive regions. The regions of programable material are configured to switch resistance upon receiving an electric pulse. An electric pulse applied between two outer electrically conductive regions of the alternating regions will switch the resistance of at least one region of programmable material. The alternating regions may include a plurality of the electrically conducting regions and a region of the programable material disposed between each of the plurality of electrically conductive regions. The resistance of each of the regions of programable material is selectively variable in at least a portion thereof as a result of the electric pulse flowing therethrough. The resistance value of the programable material region may be a readable value as a state of the device. The regions of programmable material may be formed of a phase change material or an oxide.

Abstract: A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.

Abstract: Circuit board inspection by receiving a near infrared (NIR) image of at least a portion of a circuit board, analyzing the NIR image using a machine learning model, and detecting anomalous circuit board portions according to the analysis.

Abstract: System and method to localize a position of an RRAM filament of resistive memory device at very low bias voltages using a scanning laser beam. The approach is non-invasive and allows measurement of a large number of devices for creating statistics relating to the filament formation. A laser microscope system is configured to perform a biasing the RRAM cell with voltage (or current). Concurrent to the applied bias, a laser beam is generated and aimed at different positions of the RRAM cell (e.g., by a raster scanning). Changes in the current (or voltage) flowing through the cell are measured. The method creates a map of the current (or voltage) changes at the different laser positions and detects a spot in the map corresponding to higher (or lower) current (or voltage). The method determines the (x,y) position of the spot compared to the edge/center of the RRAM cell.

Abstract: A physical unclonable function device includes alternating regions of programable material and electrically conductive regions. The regions of programable material are configured to switch resistance upon receiving an electric pulse. An electric pulse applied between two outer electrically conductive regions of the alternating regions will switch the resistance of at least one region of programmable material. The alternating regions may include a plurality of the electrically conducting regions and a region of the programable material disposed between each of the plurality of electrically conductive regions. The resistance of each of the regions of programable material is selectively variable in at least a portion thereof as a result of the electric pulse flowing therethrough. The resistance value of the programable material region may be a readable value as a state of the device. The regions of programmable material may be formed of a phase change material or an oxide.

Abstract: A method and apparatus related to developing electromagnetic emission and power models for a target device using photonic emissions thereof are provided. Data of photonic emissions of a target device during a first period of time with the target device in one or more modes is recorded. Data of electromagnetic emissions of the target device during the first period of time with the target device in the one or more modes is also recorded. The recorded data of the photonic emissions and the recorded data of the electromagnetic emissions are correlated to establish one or more electromagnetic emission models for the target device. The one or more electromagnetic emission models enable predictive analysis of emissions by the target device.

Abstract: Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.

Abstract: Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. Updating the time-dependent map of the emissions based on variable dwell times at respective locations of the DUT.

Abstract: Circuit board inspection by receiving a near infrared (NIR) image of at least a portion of a circuit board, analyzing the NIR image using a machine learning model, and detecting anomalous circuit board portions according to the analysis.

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to update the time-dependent map of the emissions based on combinations of the emissions of light at certain locations.

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

Abstract: A method for characterizing an integrated circuit that selecting at least two devices from an integrated circuit for measuring light emission, wherein each of the at least two devices have experienced a different level of stress, applying power to the integrated circuit, and measuring the light emission from the at least two devices. The method also includes comparing the light emission that is measured from the at least two devices, wherein a difference between the light emission that is measured from the at least two devices greater than a predetermined ratio indicates that at least one of the devices from the at least two devices has a below specification performance.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.