Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: Systems, computer-implemented methods, and computer program products to focus a microscope. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analyzer component that can analyze sub-images of respective sample images to identify one or more sub-images having a maximized variance of a gradient derivative corresponding to the one or more sub-images. The respective sample images can be acquired at one or more focal positions along an optical axis of a microscope. The computer executable components can further comprise a selection component that can select an image, from the respective sample images, that comprises the one or more sub-images identified. The computer executable components can also comprise a focus component that, based on a focal position corresponding to the image selected, can focus the microscope to the focal position.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: A method for characterizing an integrated circuit that selecting at least two devices from an integrated circuit for measuring light emission, wherein each of the at least two devices have experienced a different level of stress, applying power to the integrated circuit, and measuring the light emission from the at least two devices. The method also includes comparing the light emission that is measured from the at least two devices, wherein a difference between the light emission that is measured from the at least two devices greater than a predetermined ratio indicates that at least one of the devices from the at least two devices has a below specification performance.

Abstract: One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: A method for automated scan chain diagnostics includes segmenting an image of a device associated with a design layout to allocate pixels to individual design elements, comparing actual emission signatures for the individual design elements to expected emission signatures, and determining whether the actual emission signatures differ from the expected emission signatures by more than a threshold amount to determine if a defect is present.

Abstract: Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.

Abstract: Methods and systems for automated diagnostics include registering an image of a device under test (DUT) to a corresponding design layout. The image is segmented based on the registration to allocate pixels to individual design elements. Emission signatures for the individual design elements are compared to expected signatures. If the emissions differ from the expected signatures more than a threshold amount to determine if a defect is present.

Abstract: A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

Abstract: A method and system of monitoring a reliability of a semiconductor circuit are provided. A current consumption of a first ring oscillator that is in static state is measured at predetermined intervals. Each measured current consumption value is stored. A baseline current consumption value of the first ring oscillator is determined based on the stored current consumption values. A latest measured current consumption value of the first ring oscillator is compared to the baseline current consumption value. Upon determining that the latest measured current consumption value is above a threshold deviation from the baseline current consumption value, the first ring oscillator is identified to have a dielectric breakdown degradation.

Abstract: A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.

Abstract: A computer-implemented method includes receiving a plurality of images from a device under test (DUT), whereby each of the plurality of images is generated by operating the DUT at different frequency conditions. The computer-implemented method further includes receiving emission intensity values from a corresponding pixel location on each of the received plurality of images, receiving an electrical leakage current parameter for the DUT that corresponds to a change in leakage current based on a change in temperature, and receiving a temperature parameter for the DUT that corresponds to an ambient temperature value at which the DUT is maintained. A temperature value at the corresponding pixel location is then determined based on the different frequency conditions, the emission intensity values associated with the different frequency conditions, the electrical leakage current parameter, and the ambient temperature value.

Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Abstract: Methods for testing the resolution of an imaging device include forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size. The semiconductor devices are activated by providing an input signal. Light emissions from one or more of the activated semiconductor devices are suppressed by providing one or more select signals.