Patents by Inventor Frank Daeche

Frank Daeche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210127490
    Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Inventors: Petteri Palm, Martin Benisek, Liu Chen, Frank Daeche, Josef Maerz
  • Publication number: 20210036610
    Abstract: A method of manufacturing a power semiconductor system includes providing a power module having one or more power transistor dies and attaching an inductor module to the power module such that the inductor module is electrically connected to a node of the power module. The inductor module includes a substrate with a magnetic material and windings at one or more sides of the substrate. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10833583
    Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20200279799
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Application
    Filed: January 29, 2020
    Publication date: September 3, 2020
    Inventors: Dirk AHLERS, Frank DAECHE, Daniel SCHLEISSER, Thomas STOEK
  • Publication number: 20200212798
    Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10601314
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20200035645
    Abstract: A chip assembly includes a carrier and a metal grid array having an opening. The metal grid array is attached to the carrier by an attachment material. The metal grid array and the carrier define a cavity which is formed by the opening and the carrier. The chip assembly further includes an electronic chip mounted in the cavity.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 30, 2020
    Inventors: Alexander Heinrich, Frank Daeche
  • Patent number: 10325834
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Publication number: 20190081562
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10186481
    Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Frank Daeche, Zeeshan Umar
  • Publication number: 20170365539
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Application
    Filed: August 9, 2017
    Publication date: December 21, 2017
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Patent number: 9773719
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 26, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Publication number: 20170271260
    Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Applicant: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Frank Daeche, Zeeshan Umar
  • Patent number: 9437548
    Abstract: Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: September 6, 2016
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Henrik Ewe, Anton Prueckl, Joachim Mahler, Frank Daeche, Josef Hoeglauer, Riccardo Pittassi
  • Patent number: 9425116
    Abstract: An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 23, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Frank Daeche
  • Patent number: 9269685
    Abstract: An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: February 23, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Frank Daeche
  • Patent number: 9236362
    Abstract: An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 12, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Frank Daeche
  • Publication number: 20150279783
    Abstract: Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip.
    Type: Application
    Filed: June 16, 2015
    Publication date: October 1, 2015
    Inventors: Henrik Ewe, Anton Prueckl, Joachim Mahler, Frank Daeche, Josef Hoeglauer, Riccardo Pittassi
  • Patent number: 9105562
    Abstract: An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 11, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Frank Daeche
  • Patent number: 9059155
    Abstract: Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 16, 2015
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Henrik Ewe, Anton Prueckl, Joachim Mahler, Frank Daeche, Josef Hoeglauer, Riccardo Pittassi