Abstract: In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

Abstract: An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step.

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Abstract: A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi-state FET device. This device would have two different threshold voltages (V.sub.T), one where the central portion would turn on first, followed by the edges for the entire gate width to be active to give a second level of current flow. Such devices would be useful in building very compact or high density multi-state read-only-memories (ROMs).

Abstract: A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.