Patents by Inventor Frank Lehnert
Frank Lehnert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10353825Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: GrantFiled: June 16, 2017Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Patent number: 10353828Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: GrantFiled: November 13, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Patent number: 10289562Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.Type: GrantFiled: June 15, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Thomas Köhler, Frank Lehnert
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Patent number: 10248575Abstract: Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: GrantFiled: February 20, 2018Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Patent number: 10176002Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.Type: GrantFiled: December 17, 2014Date of Patent: January 8, 2019Assignee: International Business Machines CorporationInventors: Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Publication number: 20180365165Abstract: Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: ApplicationFiled: December 28, 2017Publication date: December 20, 2018Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Publication number: 20180365166Abstract: Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: ApplicationFiled: February 20, 2018Publication date: December 20, 2018Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Publication number: 20180365169Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.Type: ApplicationFiled: June 15, 2017Publication date: December 20, 2018Inventors: Uwe Brandt, Markus Helms, Thomas Köhler, Frank Lehnert
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Publication number: 20180365171Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.Type: ApplicationFiled: November 14, 2017Publication date: December 20, 2018Inventors: Uwe Brandt, Markus Helms, Thomas Köhler, Frank Lehnert
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Publication number: 20180365162Abstract: Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Publication number: 20180357181Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: ApplicationFiled: June 7, 2017Publication date: December 13, 2018Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Publication number: 20180357182Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: ApplicationFiled: November 13, 2017Publication date: December 13, 2018Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Publication number: 20180276138Abstract: A translation engine for a processor system to translate virtual memory addresses to physical addresses of a main memory of a computer system is provided, where a sequence of accesses to multiple address translation tables is performed to support a computer system virtualization level. The translation engine includes: a first pipeline having at least, a first pipeline stage to receive a value for an original address or an address translation table entry requested in a previous pass through the first pipeline; a second pipeline stage using the value as an operand in a translation operation eventually yielding the address translation result or yielding a table index to an entry in a next address translation table; and a third pipeline stage issuing a read request for the entry in the next address translation table.Type: ApplicationFiled: March 22, 2017Publication date: September 27, 2018Inventors: Uwe BRANDT, Markus HELMS, Christian JACOBI, Markus KALTENBACH, Thomas KOEHLER, Frank LEHNERT
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Patent number: 10083124Abstract: A translation engine for a processor system to translate virtual memory addresses to physical addresses of a main memory of a computer system is provided, where a sequence of accesses to multiple address translation tables is performed to support a computer system virtualization level. The translation engine includes: a first pipeline having at least, a first pipeline stage to receive a value for an original address or an address translation table entry requested in a previous pass through the first pipeline; a second pipeline stage using the value as an operand in a translation operation eventually yielding the address translation result or yielding a table index to an entry in a next address translation table; and a third pipeline stage issuing a read request for the entry in the next address translation table.Type: GrantFiled: March 22, 2017Date of Patent: September 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Publication number: 20180260336Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: ApplicationFiled: March 9, 2017Publication date: September 13, 2018Inventors: Uwe BRANDT, Markus HELMS, Christian JACOBI, Markus KALTENBACH, Thomas KOEHLER, Frank LEHNERT
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Publication number: 20180260337Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: ApplicationFiled: October 31, 2017Publication date: September 13, 2018Inventors: Uwe BRANDT, Markus HELMS, Christian JACOBI, Markus KALTENBACH, Thomas KOEHLER, Frank LEHNERT
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Publication number: 20180238463Abstract: An actuator (1) comprises an electric motor (11) for moving an actuated part (2) to an actuated position. The actuator (1) further comprises a controller (10) connected to the electric motor (11) and configured to determine a motor current of the electric motor (11) and to detect motor rotations. The controller (10) is further configured to determine the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of a load torque, and by not counting motor rotations detected while the motor current is below said current threshold.Type: ApplicationFiled: September 8, 2016Publication date: August 23, 2018Applicant: BELIMO HOLDING AGInventors: Marc THUILLARD, Stefan MISCHLER, Frank LEHNERT
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Patent number: 10025608Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.Type: GrantFiled: November 17, 2014Date of Patent: July 17, 2018Assignee: International Business Machines CorporationInventors: Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Patent number: 9845965Abstract: Disclosed is an HVAC (heating, ventilation and air-conditioning) system which comprises a fluid flow duct (1), a fluid flow valve (7) which is arranged therein and has a valve body (5) in the fluid flow duct (1) and a valve motor (15) which moves the valve body (5), a control circuit for activating the valve motor, a sensor (8) in the fluid flow duct (1) and an evaluation module for evaluating signals of the sensor. To produce an automated functional control, the following procedure is adopted: a first actuation signal is preset for the valve motor by the control circuit, and the actuation signal corresponds to a first setpoint position of the valve body (5), registration of a first signal of the sensor (8) by the evaluation module, and determination of a functional diagnosis of the fluid flow valve on the basis of the first signal of the sensor.Type: GrantFiled: April 11, 2012Date of Patent: December 19, 2017Assignee: Belimo Holding AGInventors: Frank Lehnert, Peter Schmidlin
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Patent number: 9760511Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.Type: GrantFiled: October 8, 2014Date of Patent: September 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller, Christian Jacobi, Jeffrey P. Kubala, Frank Lehnert, Bernd Nerz, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel