Patents by Inventor Frank W. Mont
Frank W. Mont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11610839Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.Type: GrantFiled: October 29, 2019Date of Patent: March 21, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Tung-Hsing Lee, Teng-Yin Lin, Frank W. Mont, Edward J. Gordon, Asmaa Elkadi, Alexander Martin, Won Suk Lee, Anvitha Shampur
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Patent number: 11362177Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.Type: GrantFiled: January 28, 2020Date of Patent: June 14, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
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Patent number: 11205699Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.Type: GrantFiled: October 17, 2019Date of Patent: December 21, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Julien Frougier, Ali Razavieh
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Patent number: 11088291Abstract: An anti-reflection coating has an average total reflectance of less than 10%, for example less than 5.9% such as from 4.9% to 5.9%, over a spectrum of wavelengths of 400-1100 nm and a range of angles of incidence of 0-90 degrees with respect to a surface normal of the anti-reflection coating. An anti-reflection coating has a total reflectance of less than 10%, for example less than 6% such as less than 4%, over an entire spectrum of wavelengths of 400-1600 nm and an entire range of angles of incidence of 0-70 degrees with respect to a surface normal of the anti-reflection coating.Type: GrantFiled: July 22, 2016Date of Patent: August 10, 2021Assignee: Rensselaer Polytechnic InstituteInventors: Sameer Chhajed, Jong Kyu Kim, Shawn-Yu Lin, Mei-Ling Kuo, Frank W. Mont, David J. Poxson, E. Fred Schubert, Martin F. Schubert
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Publication number: 20210233999Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.Type: ApplicationFiled: January 28, 2020Publication date: July 29, 2021Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
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Publication number: 20210125922Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.Type: ApplicationFiled: October 29, 2019Publication date: April 29, 2021Inventors: Tung-Hsing LEE, Teng-Yin LIN, Frank W. MONT, Edward J. GORDON, Asmaa ELKADI, Alexander MARTIN, Won Suk LEE, Anvitha SHAMPUR
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Publication number: 20210118993Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Julien Frougier, Ali Razavieh
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Patent number: 10957588Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: October 25, 2016Date of Patent: March 23, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10937694Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: July 5, 2019Date of Patent: March 2, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10903118Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: July 5, 2019Date of Patent: January 26, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10679937Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.Type: GrantFiled: October 17, 2017Date of Patent: June 9, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
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Patent number: 10658176Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.Type: GrantFiled: September 6, 2018Date of Patent: May 19, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank W. Mont, Han You, Shariq Siddiqui, Brown C. Peethala
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Patent number: 10636698Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.Type: GrantFiled: March 26, 2019Date of Patent: April 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
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Patent number: 10636656Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.Type: GrantFiled: April 16, 2018Date of Patent: April 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Lei Sun, Xunyuan Zhang, Frank W. Mont, Shao Beng Law
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Publication number: 20200083040Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: Frank W. Mont, Han You, Shariq Siddiqui, Brown C. Peethala
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Publication number: 20190333813Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Mark L. LENHARDT, Frank W. MONT, Brown C. PEETHALA, Shariq SIDDIQUI, Jessica P. STRISS, Douglas M. TRICKETT
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Publication number: 20190333814Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Mark L. LENHARDT, Frank W. MONT, Brown C. PEETHALA, Shariq SIDDIQUI, Jessica P. STRISS, Douglas M. TRICKETT
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Publication number: 20190318927Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.Type: ApplicationFiled: April 16, 2018Publication date: October 17, 2019Inventors: Lei Sun, Xunyuan Zhang, Frank W. Mont, Shao Beng Law
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Patent number: 10388565Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: May 17, 2018Date of Patent: August 20, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Publication number: 20190221473Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan