Patents by Inventor Frank W. Mont
Frank W. Mont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262892Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.Type: GrantFiled: November 8, 2016Date of Patent: April 16, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
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Patent number: 10157833Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.Type: GrantFiled: May 23, 2017Date of Patent: December 18, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Dongfei Pei, Frank W. Mont
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Publication number: 20180342454Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.Type: ApplicationFiled: May 23, 2017Publication date: November 29, 2018Inventors: Xunyuan Zhang, Dongfei Pei, Frank W. Mont
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Publication number: 20180308752Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Xunyuan Zhang, Frank W. Mont, Sean X. Lin, Mark V. Raymond
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Publication number: 20180269103Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: ApplicationFiled: May 17, 2018Publication date: September 20, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Mark L. LENHARDT, Frank W. MONT, Brown C. PEETHALA, Shariq SIDDIQUI, Jessica P. STRISS, Douglas M. TRICKETT
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Patent number: 10062560Abstract: Aspects of the present disclosure provide a method of cleaning a semiconductor device. The method includes providing a semiconductor wafer having an exposed cobalt surface and rinsing the exposed cobalt surface with cathode water having a pH greater than 9 and an oxidation reduction potential of less than 0.0.Type: GrantFiled: April 26, 2017Date of Patent: August 28, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Kevin J. Ryan, Shariq Siddiqui, Frank W. Mont, Cornelius B. Peethala
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Patent number: 10056291Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.Type: GrantFiled: November 23, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shao Beng Law, Xunyuan Zhang, Frank W. Mont, Genevieve Beique, Lei Sun
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Patent number: 10056292Abstract: Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal layer is formed on an area of the metal hardmask layer exposed by an opening in the patterned layer. After the metal layer is formed, the patterned layer is removed from the metal hardmask layer. After the patterned layer is removed, the metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.Type: GrantFiled: November 22, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Shao Beng Law, Genevieve Beique, Frank W. Mont, Lei Sun, Xunyuan Zhang
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Patent number: 10032668Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: January 23, 2017Date of Patent: July 24, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Publication number: 20180144979Abstract: Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal layer is formed on an area of the metal hardmask layer exposed by an opening in the patterned layer. After the metal layer is formed, the patterned layer is removed from the metal hardmask layer. After the patterned layer is removed, the metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.Type: ApplicationFiled: November 22, 2016Publication date: May 24, 2018Inventors: Shao Beng Law, Genevieve Beique, Frank W. Mont, Lei Sun, Xunyuan Zhang
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Publication number: 20180144976Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.Type: ApplicationFiled: November 23, 2016Publication date: May 24, 2018Inventors: Shao Beng LAW, Xunyuan ZHANG, Frank W. MONT, Genevieve BEIQUE, Lei SUN
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Publication number: 20180130699Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.Type: ApplicationFiled: November 8, 2016Publication date: May 10, 2018Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
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Patent number: 9947547Abstract: An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or bases to a substrate including exposed cobalt metal. The process can be utilized to form recesses where desired such as may be implemented for metal contact fill, metal gate fill, interconnect fill, or the like.Type: GrantFiled: June 29, 2016Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frank W. Mont, Cornelius Brown Peethala, Shariq Siddiqui, Randolph F. Knarr
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Publication number: 20180040555Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.Type: ApplicationFiled: October 17, 2017Publication date: February 8, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Xunyuan ZHANG, Frank W. MONT, Errol Todd RYAN
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Publication number: 20180005839Abstract: An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or bases to a substrate including exposed cobalt metal. The process can be utilized to form recesses where desired such as may be implemented for metal contact fill, metal gate fill, interconnect fill, or the like.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Frank W. Mont, Cornelius Brown Peethala, Shariq Siddiqui, Randolph F. Knarr
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Publication number: 20170345766Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Xunyuan ZHANG, Frank W. MONT, Errol Todd RYAN
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Publication number: 20170345752Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Xunyuan ZHANG, Frank W. MONT, Errol Todd RYAN
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Patent number: 9831174Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.Type: GrantFiled: May 31, 2016Date of Patent: November 28, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
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Patent number: 9831124Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes: a cobalt metallization structure with a modified surface of etch chemistries; a layer of material on the modified surface; and an interconnect structure in direct contact with the material.Type: GrantFiled: October 28, 2016Date of Patent: November 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Frank W. Mont
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Patent number: 9799559Abstract: A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.Type: GrantFiled: May 19, 2016Date of Patent: October 24, 2017Assignees: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Shariq Siddiqui, Frank W. Mont, Xunyuan Zhang, Brown Peethala, Douglas M. Trickett