Abstract: A solid state memory-based mass storage device and a method of transferring data between a memory controller and at least one memory device of the mass storage device through optical input/output links that transmit multiplexed optical data signals between the memory device and controller.

Abstract: A solid state drive having a non-volatile memory device and methods of operating the solid state drive to compare existing data stored on the memory device to subsequent data in an incoming data stream received by the solid state drive from a host system. If matching data are found, the solid state drive uses the existing data instead of writing the subsequent data to the memory device. Common data patterns can be shared among different files stored on the memory device.

Abstract: Solid-state mass storage devices, host computer systems, and methods of increasing the endurance of non-volatile solid-state memory components used therein. The memory components comprise memory cells organized in functional units that are adapted to receive units of data transferred from the host computer system and correspond to the functional units of the memory component. The level of programming for each cell is reduced by performing an analysis of the bit values of the units of data to be written to at least a first of the functional units of the memory component. Depending on the analysis of “0” and “1” bit values of the units of data to be written, the bit values are inverted before writing the units of data to the first memory component.

Abstract: A system and method for monitoring power consumption of a computer system component, such as a central processing unit (CPU), of a desktop computer system. The component is supplied with supply power from a power supply unit of the computer through a power supply cable. A coupling is disposed between the power supply unit and a substrate (e.g., motherboard) on which the component is mounted, and is electrically connected to at least one power supply line of the power supply cable and a power supply connector on the substrate. The power supply line carries a supply voltage. The current flow through the power supply line is determined, a power consumption reading for the component is generated based on the supply voltage and the current flow through the power supply line, and the supply voltage on the power supply line is modulated to determine a lowest current flow therethrough.

Abstract: A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface.

Abstract: A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance.

Abstract: Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.

Abstract: The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth. These optimizations in the SPD allow for much better bandwidth in real world applications.

Abstract: A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.

Abstract: Methods and systems for mass storage of data over two or more tiers of mass storage media that include nonvolatile solid-state memory devices, hard disk devices, and optionally volatile memory devices or nonvolatile MRAM in an SDRAM configuration. The mass storage media interface with a host through one or more PCIe lanes on a single printed circuit board.

Abstract: A biosignal-computer-interface apparatus and method. The apparatus includes one or more devices for generating biosignals based on at least one physiological parameter of an individual, and a computer-interface device capable of performing multiple tasks, including converting the biosignals into at least one input signal, establishing a scale encompassing different levels of the input signal, multiplying the input signal into parallel control channels, dividing the scale into multiple zones for each of the parallel control channels, assigning computer commands to each individual zone of the multiple zones, and generating the computer command assigned to at least one of the individual zones if the level of the input signal is within the at least one individual zone. The individual zones can be the same or different among the parallel control channels.

Abstract: Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.

Abstract: A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.

Abstract: A modular mass storage device suitable for use with computers and other processing apparatuses. The mass storage device includes a controller board having a system interface connector, a memory controller, a cache device, and a second connector. The mass storage device further includes a daughter board having at least one non-volatile memory device for data storage, a read-only memory device containing firmware of the mass storage device, and a daughter board connector configured to mate with the second connector of the controller board and thereby form command, address and data paths between the memory controller and the memory device of the daughter board. The memory controller and the memory device are configured so that the memory controller reads the firmware of the read-only memory device when the daughter board connector is mated with the second connector of the controller board.

Abstract: A cooling device for cooling an electronic component. The device has an enclosure adapted to contain a liquid coolant. The enclosure has an internal channel system comprising a cavity adjacent the electronic component, a first group of arborizing channels adapted to carry the liquid coolant away from the cavity, a second group of arborizing channels adapted to carry the liquid coolant to the cavity, and a plenum fluidically connecting the first and seconds groups of arborizing channels. Each group of arborizing channels has a parent branch and multiple successive sets of daughter branches with successively smaller cross-sectional areas, wherein the sum of the cross-sectional areas of the daughter branches of any set is approximately the same as that of its parent branch. Distal sets of the daughter branches are most distant from the cavity, fluidically connected to the plenum, and have the smallest cross-sectional areas of the daughter branches.

Abstract: A central processing unit (CPU) adapted for use in a computing system, such as a personal computer or other processing apparatus. The CPU is implemented to perform hyper-threading (HT), and further enables switching between HT-enabled and HT-disabled modes on the fly (without rebooting the apparatus) based on, for example, performance measurements or entries into a local library.

Abstract: Methods and systems capable of capitalizing on fast access capabilities (low initial access latencies) of nonvolatile memory technologies for use in a host system, such as computers and other processing apparatuses. The host system has a central processing unit, processor cache, and a system main memory. The system main memory includes first and second memory slots, a volatile memory subsystem having at least one DRAM-based memory module received in the first memory slot and addressed by the central processing unit, and a nonvolatile memory subsystem having at least a first nonvolatile-based memory module in the second memory slot and addressed by the central processing unit. At least one memory controller is integrated onto the central processing unit for controlling the processor cache, the volatile memory subsystem, and the nonvolatile memory subsystem.

Abstract: A system (10) and method for monitoring power consumption of a computer system component, such as a central processing unit (CPU), of a desktop computer system. The component is supplied with supply power from a power supply unit (22) of the computer through a power supply cable (14). A coupling (12) is disposed between the power supply unit (22) and a substrate (e.g., motherboard) on which the component is mounted, and is electrically connected to at least one power supply line (18) of the power supply cable (14) and a power supply connector (24) on the substrate (20). The power supply line (18) carries a supply voltage, and one or more devices (26,34,36,46) associated with the coupling (12) determine current flow through the power supply line (18) and provide a power consumption reading for the component based on the supply voltage and the current flow through the power supply line (18).

Abstract: A mass storage device and method that utilize storage memory and a shadow memory capable of increasing the speed associated with copying data from one location to another location within the storage memory without the need to access a host computer for the copy transaction. A controller of the mass storage device receives a file copy request for a file to be copied between first and second locations within the storage memory. Data from the first location within the storage memory is then loaded into a shadow memory means of the mass storage device, and then the data is written from the shadow memory means to the second location within the storage memory.

Abstract: A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.