Abstract: A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device.

Abstract: RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value.

Abstract: A method of maintaining a solid-state drive so that free space within memory blocks of the drive becomes free usable space to the drive. The drive comprises cells organized in pages that are organized in memory blocks in which at least user files are stored. A defragmentation utility is executed to cause at least some of the memory blocks that are partially filled with data and contain file fragments to be combined or aligned and to cause at least some of the memory blocks that contain only invalid data to be combined or aligned. A block consolidation utility is then executed to eliminate at least some of the partially-filled blocks by consolidating the file fragments into a fewer number of the memory blocks. The consolidation utility also increases the number of memory blocks that contain only invalid memory. All of the memory blocks containing only invalid data are then erased.

Abstract: A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory components are periodically heated above an intrinsic operating temperature thereof to a preselected temperature that is sufficient to thermally recondition the memory component in a manner that increases the write endurance of the memory component.

Abstract: A mass storage device configured to enable accessing of an array of solid-state memory devices on the storage device in the event of a memory controller failure on the storage device. The storage device includes a printed circuit board, an array of non-volatile solid-state memory devices on the printed circuit board, a system interface connector on the printed circuit board and adapted to connect the mass storage device to a host system, and an onboard memory controller on the printed circuit board and adapted to communicate between the host system and the memory devices. The mass storage device further includes an auxiliary connector on the printed circuit board that is separate from and in addition to the system interface connector. The auxiliary connector provides a direct path for accessing the memory devices that is separate from the onboard memory controller.

Abstract: Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system.

Abstract: A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses.

Abstract: Non-volatile storage devices and methods capable of achieving large capacity SSDs containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and optionally a memory controller. The bank switching circuitry is functionally interposed between the banks of memory devices and either the connector or the memory controller. The bank switching circuitry operates to switch accesses by a system logic or the memory controller among the at least two banks.

Abstract: A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.

Abstract: A nonvolatile memory device and method using phase changes in a substrate to alter optical properties of the substrate for the purpose of data storage. The memory device includes a substrate containing a phase change material having phases comprising amorphous and crystalline phases. The phase change material has optical properties that change depending on whether the phase change material is in the amorphous phase or the crystalline phase. The memory device is further equipped with one or more devices that generate light and transmit the light into the substrate, and one or more devices that cause the phase change material to change between the amorphous and crystalline phases thereof. At least one optical sensing device detects light that passes into the phase change material to the optical sensing device and generates electrical signals based thereon, which are converted into bit values if they exceed a threshold.

Abstract: Methods, systems and devices for increasing the reliability of solid state drives containing one or more NAND flash memory arrays. The methods, systems and devices take into account usage patterns that can be employed to initiate proactive scrubbing on demand, wherein the demand is automatically generated by a risk index that can be based on one or more of various factors that typically contribute to loss of data retention in NAND flash memory devices.

Abstract: A non-volatile memory-based mass storage device that includes a host interface attached to a package, at least one non-volatile memory device within the package, a memory controller connected to the host interface and adapted to access the non-volatile memory device in a random access fashion through a parallel bus, a volatile memory cache within the package, and co-processor means within the package for performing hardware-based compression of cached data before writing the cached data to the non-volatile memory device in random access fashion and performing hardware-based decompression of data read from the non-volatile memory device in random access fashion.

Abstract: A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements.

Abstract: A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.

Abstract: A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior space above the planar body.

Abstract: A method and mass storage device that combine multiple solid state drives (SSDs) to a single volume. The device includes a carrier board and at least two solid state drives having power and data connections to the carrier board. The carrier board includes a circuit board functionally connected to a control logic and at least two secondary connectors that are disposed at different edges of the circuit board and functionally connected to the control logic. The solid state drives are connected to the carrier board through the secondary connectors, and each solid state drive has a power and data connector directly connected to one of the secondary connectors of the carrier board. The solid state drives are oriented substantially parallel to the carrier board and to each other.

Abstract: A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

Abstract: A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior space above the planar body.

Abstract: Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.

Abstract: A biosignal-computer-interface apparatus and method. The apparatus includes one or more devices for generating biosignals based on at least one physiological parameter of an individual, and a computer-interface device capable of performing multiple tasks, including converting the biosignals into at least one input signal, establishing a scale encompassing different levels of the input signal, multiplying the input signal into parallel control channels, dividing the scale into multiple zones for each of the parallel control channels, assigning computer commands to each individual zone of the multiple zones, and generating the computer command assigned to at least one of the individual zones if the level of the input signal is within the at least one individual zone. The individual zones can be the same or different among the parallel control channels.