Abstract: A phase change memory device is disclosed, including a substrate. The phase change memory also includes a bottom electrode. A conductive structure with a cavity is provided to electrically contact the bottom electrode, wherein the conductive structure includes sidewalls with different thicknesses. A phase change spacer is formed to cross the sidewalls with different thicknesses. A top electrode is electrically contacted to the phase change spacer.

Abstract: A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer.

Abstract: A method for forming patterns comprises providing a substrate. A set of seed features is formed over the substrate. At least one bi-layer comprising a first layer followed by a second layer is formed on the set of seed features. The first layer and the second layer above the set of seed features are removed. The first layer and the second layer are anisotropically etched successively at least one time to form an opening next to the set of seed features.

Abstract: Methods for reading a memory cell are provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data. The first digital data is stored in a shift register. A second read pulse is applied to the memory cell, heating the memory cell to a second temperature and obtaining a second read data. The second read data is converted to a second digital data. The second digital data is stored in the shift register. A ratio of the first digital data and the second digital data is calculated, obtaining a quotient. The quotient is converted to an analog value. A log amplifier circuit takes the log of the analog value, representing an activation energy state.

Abstract: A phase-change memory element is provided. The phase-change memory element includes: a first electrode formed on a substrate; a first dielectric layer, with an opening, formed on the first electrode, wherein the opening exposes a top surface of the first electrode; a pillar structure formed directly on the first electrode within the opening; an inner phase-change material layer surrounding the pillar structure, directly contacting the first electrode; a second dielectric layer surrounding the inner phase-change material layer; an outer phase-change material layer surrounding the second dielectric layer; a phase-change material collar formed between the second dielectric layer and the first electrode, connecting the inner phase-change material layer with the outer phase-change material layer; and a second electrode formed directly on the pillar structure, directly contacting the top surface of the inner phase-change material layer.

Abstract: A phase-change memory element is provided. The phase-change memory element includes: a first electrode formed on a substrate; a first dielectric layer, with an opening, formed on the first electrode, wherein the opening exposes a top surface of the first electrode; a pillar structure formed directly on the first electrode within the opening; an inner phase-change material layer surrounding the pillar structure, directly contacting the first electrode; a second dielectric layer surrounding the inner phase-change material layer; an outer phase-change material layer surrounding the second dielectric layer; a phase-change material collar formed between the second dielectric layer and the first electrode, connecting the inner phase-change material layer with the outer phase-change material layer; and a second electrode formed directly on the pillar structure, directly contacting the top surface of the inner phase-change material layer.

Abstract: A method of photolithographic exposure is disclosed. The photolithographic exposure method comprises providing a substrate, forming a first resist layer thereon, forming a second resist layer on the first resist layer, the second resist layer providing a transmission which first increases then decreases as exposure dose increases, and exposing the second resist layer.

Abstract: A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.

Abstract: The invention is directed to a resistive memory cell on a substrate. The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element. The first gate and the second gate are separately disposed on the substrate. Notably, the first length of the first gate is different from the second length of the second gate. Furthermore, the common doped region of the first gate and the second gate is disposed in the substrate. The contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate. Moreover, the resistive memory element is connected between the contact plug and the bit line.

Abstract: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.

Abstract: A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer.

Abstract: A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer.

Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Abstract: A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal.

Abstract: A phase change memory device is disclosed, including a substrate. The phase change memory also includes a bottom electrode. A conductive structure with a cavity is provided to electrically contact the bottom electrode, wherein the conductive structure includes sidewalls with different thicknesses. A phase change spacer is formed to cross the sidewalls with different thicknesses. A top electrode is electrically contacted to the phase change spacer.

Abstract: A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor.

Abstract: A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer.

Abstract: A phase-change memory element. The phase-change memory element comprises a first electrode and a second electrode. A first phase change layer is electrically coupled to the first electrode. A second phase change layer is electrically coupled to the second electrode. A conductive bridge is formed between and electrically coupled to the first and second phase change layers.

Abstract: A method for forming patterns comprises providing a substrate. A set of seed features is formed over the substrate. At least one bi-layer comprising a first layer followed by a second layer is formed on the set of seed features. The first layer and the second layer above the set of seed features are removed. The first layer and the second layer are anisotropically etched successively at least one time to form an opening next to the set of seed features.

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer.