Patents by Inventor Fredrick B. Jenne

Fredrick B. Jenne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190198329
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.
    Type: Application
    Filed: January 4, 2019
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 10199229
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Publication number: 20180351003
    Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
    Type: Application
    Filed: May 24, 2018
    Publication date: December 6, 2018
    Applicant: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 10032517
    Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: July 24, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
  • Publication number: 20180166140
    Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.
    Type: Application
    Filed: April 15, 2015
    Publication date: June 14, 2018
    Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
  • Patent number: 9997641
    Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 12, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Publication number: 20180053657
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 22, 2018
    Applicant: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 9899089
    Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: February 20, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
  • Patent number: 9793125
    Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 17, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 9748103
    Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 29, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Publication number: 20160300959
    Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
    Type: Application
    Filed: February 23, 2016
    Publication date: October 13, 2016
    Inventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 9355849
    Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 31, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sam G. Geha
  • Publication number: 20160141180
    Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Application
    Filed: August 11, 2015
    Publication date: May 19, 2016
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Publication number: 20160005475
    Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.
    Type: Application
    Filed: April 15, 2015
    Publication date: January 7, 2016
    Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
  • Patent number: 9105512
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 11, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 9023707
    Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 5, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Bo Jin, Fredrick B. Jenne
  • Patent number: 8993400
    Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Fredrick B. Jenne, William C. Koutny
  • Publication number: 20140374813
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described.
    Type: Application
    Filed: April 29, 2014
    Publication date: December 25, 2014
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 8679927
    Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: March 25, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Fredrick B. Jenne, Sagy Levy
  • Patent number: 8680601
    Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 25, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Levy, Fredrick B. Jenne, Krishnaswamy Ramkumar