Abstract: A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs.

Abstract: Disclosed are a method and device for programming an array of memory cells.

Abstract: A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs.

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.

Abstract: A method to eliminate over-erase in a nonvolatile trapped-charge memory array during write operations includes a three-cycle process of bulk programming the memory array, bulk erasing the memory array and selectively inhibiting one or more memory cells in the memory array while applying a programming voltage to the memory array.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: An MRAM device is provided which includes an array of magnetic elements, a plurality of conductive lines configured to set magnetization states of the magnetic elements and circuitry configured to vary current applications along one or more of the conductive lines. In some cases, the MRAM device may additionally or alternatively include circuitry which is configured to terminate an application of current along one or more of the conductive lines before magnetization states of one or more magnetic elements selected for a write operation of the device are changed. In either case, a device is provided which includes an MRAM array and a first storage circuit comprising one or more magnetic elements, wherein the first storage circuit is configured to store parameter settings characterizing operations of the magnetic random access memory array within the magnetic elements. Methods for operating the devices provided herein are contemplated as well.

Abstract: An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse including a capacitor. The capacitor may include a gate over a gate oxide and an n-well under the gate oxide. The n-well may have two n+ regions used as contact points for the n-well. Upon programming, an electrically conductive path (e.g., a short) is permanently burned through the gate oxide. The antifuse cell occupies a relatively small area while providing a relatively tight read current distribution.

Abstract: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. In another embodiment, current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. In yet another embodiment, dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.

Abstract: An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. Current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. Dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.

Abstract: A latching circuit is provided that includes a latch, a storage element, and a selection circuit coupled between the latch and the storage element. The latch can receive true and complementary voltage values from, for example, a data bus and, if called upon, forward the latched value to the non-volatile storage element via the selection circuit. Control signals sent to the selection circuit allow the latched data to be written to or read from the storage element. Once programmed, the voltage values will remain in the latching circuit even after power is removed. If the latched data is not sent to the non-volatile storage element, the latching circuit essentially functions as a volatile latch, and the data will be lost if power is removed. The switching circuit thereby operates as a dual-purpose volatile and non-volatile latching circuit that can be embodied as an array of latching circuits that temporarily and/or permanently store true and complementary data signals.

Abstract: A transistor includes a non-self-aligned gate-terminal junction in a substrate having a relatively thick oxide layer disposed between a gate region and a terminal region and a relatively thin oxide layer disposed between the gate structure and the substrate. The terminal region may be the drain region of the transistor and it may include a buried N+ region within the substrate. The transistor may be formed in a p-well. Further, the transistor may also include a self-aligned gate-terminal junction between the gate structure and a source region. In a further embodiment, a transistor fabrication method includes forming an active area in a substrate and implanting an N-type impurity into a first terminal region of the active area. An oxide layer is differentially grown over the active area so that the oxide layer has a first thickness over the first terminal region and a second thickness over the remaining portion of the active area.

Abstract: An architecture for data correction that may be used in non-volatile random access memories. In one embodiment, a circuit configured to be responsive to a control signal and to provide bitline outputs in response to bitline inputs is provided. The states of the bitline outputs depend upon the states of the bitline inputs and the control signal. The control signal may be provided by a non-volatile static random access memory (SRAM) cell. The circuit may include inverting and non-inverting paths or may include crossing and passing circuitry. The crossing and passing circuitry connects a first input of the circuit to a second output of the circuit in response to a first state of the control signal and further connects the first input to a first output of the circuit in response to a second state of the control signal. The control signal may be generated by a control device such as a non-volatile random access memory cell.

Abstract: A memory cell includes non-volatile and volatile storage elements and is configured to dynamically alter threshold voltages of the non-volatile storage elements to store states of the volatile storage elements. The volatile storage elements may be stacked gate PMOS transistors, one of which may include a gate structure having a poly-silicon control gate disposed over a poly-silicon floating gate. The control gate and floating gate may be separated by a coupling dielectric, which may be an ONO stack or a deposited oxide. The gate structure may be disposed over an active area of a substrate including a drain and a source of the PMOS transistor. The active area may be disposed in an n-well of the substrate. A first of the volatile storage elements may comprise an NMOS transistor which is formed in a p-well of the substrate. The p-well may further be disposed in an n-well.

Abstract: A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner.