Patents by Inventor Freeman L. Rawson, III

Freeman L. Rawson, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8307220
    Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8276015
    Abstract: Semiconductor device circuits and methods are provided for adjusting core processor performance based on usage metrics. Metric detection and adjustment are performed in digital logic hardware guided by registers providing maximum and minimum frequency settings, without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Power-performance drivers provide applications or the operating system ability to specify maximum and minimum frequency requirements.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8276012
    Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Heather L. Hanson, Charles R. Lefurgy, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8261112
    Abstract: A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: September 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: John B. Carter, Heather L. Hanson, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8250395
    Abstract: A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: John B. Carter, Heather L. Hanson, Karthick Rajamani, Freeman L. Rawson, III, Todd J. Rosedahl, Malcolm S. Ware
  • Publication number: 20120210152
    Abstract: A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 16, 2012
    Applicant: International Business Machines Corporation
    Inventors: Naresh Nayar, Karthik Rajamani, Freeman L. Rawson, III
  • Publication number: 20120198452
    Abstract: A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
    Type: Application
    Filed: April 12, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: RICHARD L. ARNDT, NARESH NAYAR, CHRISTOPHER FRANCOIS, KARTHICK RAJAMANI, FREEMAN L. RAWSON, III, RANDAL C. SWANBERG
  • Publication number: 20120198247
    Abstract: A method for managing energy. A processor unit identifies a plurality of groups of virtual machines in a computer system. The processor unit allocates the energy in the computer system to the plurality of groups of virtual machines based on a policy.
    Type: Application
    Filed: April 11, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Freeman L. Rawson, III
  • Publication number: 20120173906
    Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 5, 2012
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
  • Publication number: 20120144218
    Abstract: Power is allocated between processors in a multiprocessor system. A request to acquire a lock is received from a first thread executing on a first processor. Responsive to receiving the request to acquire a lock, determination is made as to whether a second thread has acquired the lock. Responsive to determining that the second thread has acquired the lock, an original frequency of the first thread executing on the first processor and an operating frequency of the second thread executing on the second processor is identified. The operating frequency of the second thread executing on the second processor is then altered based on the original frequency of the first thread executing on the first processor. When the second thread releases the lock, the spinning thread with the highest original frequency acquires the lock.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas M. Brey, Freeman L. Rawson, III
  • Publication number: 20120117403
    Abstract: A method, computer program product, and apparatus for managing power in a data processing system are presented. A core is activated in the data processing system and configured to operate at a frequency in response to receiving a request to increase a processing capacity of a set of resources in the data processing system. A determination whether a use of power resulting from activating the core configured to operate at the frequency meets a policy for the use of the power in the data processing system is made. A set of parameters associated with devices in the set of resources are adjusted to meet the policy for the use of power in the data processing system in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed per unit of time by a set of cores associated with the set of resources increased after activating the core is made.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas Bieswanger, Andrew J. Geissler, Hye-Young McCreary, Freeman L. Rawson, III, Malcolm S. Ware
  • Publication number: 20120117390
    Abstract: A method, data processing system, and computer program product for managing energy. A processor unit identifies a plurality of groups of virtual machines in a computer system. The processor unit allocates the energy in the computer system to the plurality of groups of virtual machines based on a policy.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Freeman L. Rawson, III
  • Publication number: 20120116599
    Abstract: A mechanism is provided for allocating energy budgets to a plurality of logical partitions. An overall energy budget for the data processing system and a total of a set of requested initial energy budgets for the plurality of partitions are determined. A determination is made as to whether the total of the set of requested initial energy budgets for the plurality of partitions is greater than the overall energy budget for the data processing system. Responsive to the total of the set of requested initial energy budgets exceeding the overall energy budget, an initial energy budget is allocated to each partition in the plurality of partitions based on at least one of priority or proportionality of each partition in the plurality of partitions such that a total of the initial energy budgets for the plurality of partitions does not exceed the overall energy budget of the data processing system.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Heather L. Hanson, Charles R. Lefurgy, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8171319
    Abstract: Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Soraya Ghiasi, Malcolm S. Ware, Karthick Rajamani, Freeman L. Rawson, III, Michael S. Floyd, Juan C. Rubio
  • Publication number: 20120096293
    Abstract: A mechanism is provided for directed resource folding for power management. The mechanism receives a set of static platform characteristics and a set of dynamic platform characteristics for a set of resources associated with the data processing system thereby forming characteristic information. The mechanism determines whether one or more conditions have been met for each resource in the set of resources using the characteristic information. Responsive to the one or more conditions being met, the mechanism performs a resource optimization to determine at least one of a first subset of resources in the set of resources to keep active and a second subset of resources in the set of resources to dynamically fold. Based on the resource optimization, the mechanism performs either a virtual resource optimization to optimally schedule the first subset of resources or a physical resource optimization to dynamically fold the second subset of resources.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: International Business Machines Corporation
    Inventors: Michael S. Floyd, Christopher Francois, Naresh Nayar, Karthick Rajamani, Freeman L. Rawson, III, Randal C. Swanberg, Malcolm S. Ware
  • Patent number: 8112250
    Abstract: Semiconductor device circuits and methods are provided for adjusting core processor performance and energy-efficiency based on usage metrics. Metric detection, performance state selection, and adjustment are done in digital logic hardware without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Mapping usage and state information to desired processor power-performance states is also provided in circuitry rather than firmware or power control software. The mapping values may be programmable software or firmware, but detection, selection, and adjustment occur automatically in hardware without intervening input from firmware or software.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8103884
    Abstract: Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
  • Publication number: 20110320840
    Abstract: A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: International Business Machines Corporation
    Inventors: Naresh Nayar, Karthick Rajamani, Freeman L. Rawson, III
  • Publication number: 20110296212
    Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8028183
    Abstract: Disclosed is a computer implemented method, computer program product, and apparatus for determining a safe lower bound for a commonly powered data processing system. A power management module operates the data processing system using at least one nominal operating parameter during an exploration periodicity, with the at least one nominal operating parameter being clock speed. The power management module determines whether a calibration period is occurring. The power management module calibrates the data processing system up to a measurement interval duration expiration. The power management module may repeat operating the data processing system using the at least one nominal operating parameter.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Andreas Bieswanger, Thomas M. Brey, Ajay Dholakia, Andrew Geissler, Hye-Young McCreary, Freeman L. Rawson, III, Malcolm S. Ware