Abstract: A display device includes a pixel array substrate and a circuit board. The pixel array substrate has a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. Multiple bonding pads are located on the first surface. The circuit board is bent from above the first surface of the pixel array substrate to below the second surface. The circuit board is electrically connected to the bonding pads and includes a thermoplastic substrate. The thermoplastic substrate includes a third surface facing the pixel array substrate and a fourth surface opposite to the third surface. The thermoplastic substrate includes a first bend formed by thermoplastics.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: Parasympathetic neurons (parasymN) are important for unconscious body responses, including rest-and-digest and calming the body. Disclosed herein is a chemically defined differentiation protocol that generates parasympathetic neurons from stem cells. The protocol yields high efficiency and purity cultures that are electrically active and respond to specific stimuli. Their molecular characteristics and maturation stage are described and evidence for their use as a model for studying parasymN function and dysfunction. Cell populations and compositions formed from the resulting cells, as well as methods of their use for disease treatment, drug screening, and modeling of human disorders affecting parasymN are also provided.

Abstract: A display module includes a driving substrate, a plurality of light-emitting diode (LED) lamp boards, a transparent cover and a blocking structure. The LED lamp boards are separately disposed on the driving substrate separately. The transparent cover is disposed on the driving substrate and has a plurality of accommodating grooves. The LED lamp boards correspond to the accommodating grooves respectively and are disposed at intervals. The blocking structure is disposed on the transparent cover and located between the transparent cover and the driving substrate. The LED lamp boards and the blocking structure are disposed at intervals.

Abstract: A backlight module comprises a back frame with at least one perforation, a light board arranged on the back frame, a plurality of light-emitting elements arranged on the light board at intervals, a fixing frame combined with the back frame, and a plurality of optical films stacked on the fixing frame. The light board has at least one through portion, and the position of the through portion corresponds to the at least one perforation of the back frame. A part of the fixing frame is positioned in the at least one perforation of the back frame through the at least one through portion of the light board. The effect of a narrow frame can be effectively achieved by arranging the joint part of the fixing frame and the back frame on the inner side of the back frame and forming the through portion on the edge of the light board to be engaged with the joint part of the fixing frame and the back frame. The present invention also provides a display device comprising the backlight module.

Abstract: A backlight module comprises a back frame with at least one perforation, a light board arranged on the back frame, a plurality of light-emitting elements arranged on the light board at intervals, a fixing frame combined with the back frame, and a plurality of optical films stacked on the fixing frame. The light board has at least one through portion, and the position of the through portion corresponds to the at least one perforation of the back frame. A part of the fixing frame is positioned in the at least one perforation of the back frame through the at least one through portion of the light board. The effect of a narrow frame can be effectively achieved by arranging the joint part of the fixing frame and the back frame on the inner side of the back frame and forming the through portion on the edge of the light board to be engaged with the joint part of the fixing frame and the back frame. The present invention also provides a display device comprising the backlight module.

Abstract: A heat-dissipating device includes a casing and a heat dissipating fin set. The casing has a first hole structure. The heat dissipating fin set includes a protruding fin, a sheltering component and a bridging component. A hollow chamber of the protruding fin has a first opening and a second opening adjacent to each other. The first opening is connected to an inner space of the casing. The sheltering component is disposed on the protruding fin to shelter the second opening. The bridging component is connected to the protruding fin and fixed onto the first hole structure.

Abstract: A curved backlight module includes a frame unit, a light source, and a diffuser plate. The frame unit includes a back frame, a curvature fixing member combined with the back frame, and at least one first positioning structure. The at least one first positioning structure is disposed on anyone of the back frame or the curvature fixing member. The curvature fixing member presses the diffuser plate so that at least a portion of the diffuser plate has the same curvature with the curvature fixing member. The diffuser plate has at least one second positioning structure, the at least one first positioning structure of the frame unit is combined with the at least one second positioning structure of the diffuser plate to limit the diffuser plate and simplify the structure of the positioning elements. The curvature fixing member stably maintains the curvature of the diffuser plate, thereby improving the overall structural stability and optical quality.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure.

Abstract: A sensing data accessing method and a sensing data accessing system are disclosed. The method includes: activating a shared memory; generating sensing data by a sensor; storing first sensing data among the sensing data to the shared memory and updating an operation state of the shared memory through a sensor interface; in response to an update of the operation state, reading the first sensing data from the shared memory through a software interface; and performing a default operation according to the first sensing data.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A carriers synchronizing method of a hybrid frequency parallel inverter is proposed. A low-frequency ripple simulating step is performed to drive a high-frequency controlling unit to simulate a low-frequency ripple. An equidistant grid sampling step is performed to drive the high-frequency controlling unit to sample a sample ripple to generate a sample group and sample the low-frequency ripple to generate a plurality of low-frequency reference groups. An actual shifting angle searching step is performed to drive the high-frequency controlling unit to compare the sample group with the low-frequency reference groups to search an actual shifting angle from the reference shifting angles. A high-frequency carrier adjusting step is performed to drive a proportional integral controller to calculate the actual shifting angle to generate a sync reference, and then a period counter adjusts a starting point of the high-frequency carrier according to the sync reference.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A touch display panel, including a pixel circuit substrate, a color filter substrate, and a display medium layer, is provided. The pixel circuit substrate includes pixel structures, data lines, touch sensing electrodes, touch signal lines, and at least one test circuit. Each pixel structure has an active element and a pixel electrode. The data lines are electrically connected to active elements. The touch sensing electrodes are overlapped with pixel electrodes. The touch signal lines are electrically connected to the touch sensing electrodes. The test circuit is electrically connected to at least part of the touch signal lines or the data lines and includes a peripheral line and first and second test pads. The first and second test pads are respectively disposed on a first side and a second side of a display area. The display medium layer is disposed between the pixel circuit substrate and the color filter substrate.

Abstract: An optical film is disclosed. The optical film is divided into a main body and two extending portions arranged along a second direction by two imaginary lines which are extended along a first direction and parallel to each other, wherein the second direction is substantially perpendicular to the first direction. The main body is located between the two extending portions. Each of the extending portions has an abutting edge. A first length W0 of the main body along the first direction is greater than a second length W1 of the abutting edge along the first direction.

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.