Abstract: An optical fiber transmission device includes a substrate, a photonic integrated circuit, and an optical fiber assembly. The photonic integrated circuit is disposed on an area of the substrate. The substrate has a protruding structure at an interface with an edge of the photonic integrated circuit. The optical fiber assembly includes an optical fiber and a ferrule that sleeves the optical fiber. The protruding structure of the substrate is configured to abut against the ferrule to limit the position of the optical fiber assembly in a vertical direction of the substrate, such that the protruding structure is a stopper for the optical fiber assembly in the vertical direction.

Abstract: An optical fiber network device includes a fiber and a photonic integrated circuit. Fiber receives a first optical signal and transmits a second optical signal. A first wavelength of first optical signal is different from a second wavelength of second optical signal. Photonic integrated circuit includes a laser chip, a photodetector, a wavelength division multiplexing coupler, a first optical modulation element and a second optical modulation element. Laser chip is disposed on photonic integrated circuit, and is configured to generate first optical signal. Photodetector detects second optical signal. Wavelength division multiplexing coupler is configured to couple first optical signal to fiber, and receives second optical signal. First optical modulation element is coupled to wavelength division multiplexing coupler and laser chip, and is configured to modulate first optical signal.

Abstract: Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; a

Abstract: A mobile device includes a system circuit board, a metal frame, one or more other antenna elements, a display device, a first feeding element, and an RF (Radio Frequency) module. The system circuit board includes a system ground plane. The metal frame at least includes a first portion and a second portion. The metal frame at least has a first cut point positioned between the first portion and the second portion. The metal frame further has a second cut point for separating the other antenna elements from the first portion. The first cut point is arranged to be close to a middle region of the display device. The first feeding element is directly or indirectly electrically connected to the first portion. A first antenna structure is formed by the first feeding element and the first portion.

Abstract: A thermoplastic vulcanizate is provided. The thermoplastic vulcanizate includes: (A) about 100 parts by weight of a styrene copolymer rubber; (B) about 40-90 parts by weight of a thermoplastic elastomer; (C) about 5-15 parts by weight of an interfacial compatible resin; and (D) about 0.2-3 parts by weight of a cross-linking formulation, wherein the content of component (A) is greater than the content of component (B). Component (A) is dispersed in component (B) in the form of particles with a particle size of about 0.5-10 ?m.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.

Abstract: A display module includes a driving substrate, a plurality of light-emitting diode (LED) lamp boards, a transparent cover and a blocking structure. The LED lamp boards are separately disposed on the driving substrate separately. The transparent cover is disposed on the driving substrate and has a plurality of accommodating grooves. The LED lamp boards correspond to the accommodating grooves respectively and are disposed at intervals. The blocking structure is disposed on the transparent cover and located between the transparent cover and the driving substrate. The LED lamp boards and the blocking structure are disposed at intervals.

Abstract: A backlight module comprises a back frame with at least one perforation, a light board arranged on the back frame, a plurality of light-emitting elements arranged on the light board at intervals, a fixing frame combined with the back frame, and a plurality of optical films stacked on the fixing frame. The light board has at least one through portion, and the position of the through portion corresponds to the at least one perforation of the back frame. A part of the fixing frame is positioned in the at least one perforation of the back frame through the at least one through portion of the light board. The effect of a narrow frame can be effectively achieved by arranging the joint part of the fixing frame and the back frame on the inner side of the back frame and forming the through portion on the edge of the light board to be engaged with the joint part of the fixing frame and the back frame. The present invention also provides a display device comprising the backlight module.

Abstract: A backlight module comprises a back frame with at least one perforation, a light board arranged on the back frame, a plurality of light-emitting elements arranged on the light board at intervals, a fixing frame combined with the back frame, and a plurality of optical films stacked on the fixing frame. The light board has at least one through portion, and the position of the through portion corresponds to the at least one perforation of the back frame. A part of the fixing frame is positioned in the at least one perforation of the back frame through the at least one through portion of the light board. The effect of a narrow frame can be effectively achieved by arranging the joint part of the fixing frame and the back frame on the inner side of the back frame and forming the through portion on the edge of the light board to be engaged with the joint part of the fixing frame and the back frame. The present invention also provides a display device comprising the backlight module.

Abstract: A heat-dissipating device includes a casing and a heat dissipating fin set. The casing has a first hole structure. The heat dissipating fin set includes a protruding fin, a sheltering component and a bridging component. A hollow chamber of the protruding fin has a first opening and a second opening adjacent to each other. The first opening is connected to an inner space of the casing. The sheltering component is disposed on the protruding fin to shelter the second opening. The bridging component is connected to the protruding fin and fixed onto the first hole structure.

Abstract: A curved backlight module includes a frame unit, a light source, and a diffuser plate. The frame unit includes a back frame, a curvature fixing member combined with the back frame, and at least one first positioning structure. The at least one first positioning structure is disposed on anyone of the back frame or the curvature fixing member. The curvature fixing member presses the diffuser plate so that at least a portion of the diffuser plate has the same curvature with the curvature fixing member. The diffuser plate has at least one second positioning structure, the at least one first positioning structure of the frame unit is combined with the at least one second positioning structure of the diffuser plate to limit the diffuser plate and simplify the structure of the positioning elements. The curvature fixing member stably maintains the curvature of the diffuser plate, thereby improving the overall structural stability and optical quality.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure.

Abstract: A sensing data accessing method and a sensing data accessing system are disclosed. The method includes: activating a shared memory; generating sensing data by a sensor; storing first sensing data among the sensing data to the shared memory and updating an operation state of the shared memory through a sensor interface; in response to an update of the operation state, reading the first sensing data from the shared memory through a software interface; and performing a default operation according to the first sensing data.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A carriers synchronizing method of a hybrid frequency parallel inverter is proposed. A low-frequency ripple simulating step is performed to drive a high-frequency controlling unit to simulate a low-frequency ripple. An equidistant grid sampling step is performed to drive the high-frequency controlling unit to sample a sample ripple to generate a sample group and sample the low-frequency ripple to generate a plurality of low-frequency reference groups. An actual shifting angle searching step is performed to drive the high-frequency controlling unit to compare the sample group with the low-frequency reference groups to search an actual shifting angle from the reference shifting angles. A high-frequency carrier adjusting step is performed to drive a proportional integral controller to calculate the actual shifting angle to generate a sync reference, and then a period counter adjusts a starting point of the high-frequency carrier according to the sync reference.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A touch display panel, including a pixel circuit substrate, a color filter substrate, and a display medium layer, is provided. The pixel circuit substrate includes pixel structures, data lines, touch sensing electrodes, touch signal lines, and at least one test circuit. Each pixel structure has an active element and a pixel electrode. The data lines are electrically connected to active elements. The touch sensing electrodes are overlapped with pixel electrodes. The touch signal lines are electrically connected to the touch sensing electrodes. The test circuit is electrically connected to at least part of the touch signal lines or the data lines and includes a peripheral line and first and second test pads. The first and second test pads are respectively disposed on a first side and a second side of a display area. The display medium layer is disposed between the pixel circuit substrate and the color filter substrate.

Abstract: An optical film is disclosed. The optical film is divided into a main body and two extending portions arranged along a second direction by two imaginary lines which are extended along a first direction and parallel to each other, wherein the second direction is substantially perpendicular to the first direction. The main body is located between the two extending portions. Each of the extending portions has an abutting edge. A first length W0 of the main body along the first direction is greater than a second length W1 of the abutting edge along the first direction.